Start trying to make InstCombine preserve more debug info.  The idea here is to set the debug location on the IRBuilder, which will be then right location in most cases.  This should magically give many transformations debug locations, and fixing places which are missing a debug location will usually just means changing the code creating it to use the IRBuilder.

As an example, the change to InstCombineCalls catches a common case where a call to a bitcast of a function is rewritten.

Chris, does this approach look reasonable?

llvm-svn: 131516

llvm-svn: 131512

llvm-svn: 131510

llvm-svn: 131508

take r13, so we can just make it a GPR. This fixes PR8825.

llvm-svn: 131507

were marked as taking a tGPR when in reality they take an rGPR.

llvm-svn: 131506

format.

llvm-svn: 131503

Make fast-isel miss counting in -stats and -fast-isel-verbose take terminators into account; since there are many fewer isel misses with recent changes, misses caused by terminators are more significant.

llvm-svn: 131502

llvm-svn: 131497

llvm-svn: 131495

rdar://problem/6945110

llvm-svn: 131493

vrev is incorrectly defined in the perfect shuffle table. The ordering is backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case.

llvm-svn: 131488

llvm-svn: 131482

llvm-svn: 131481

llvm-svn: 131480

llvm-svn: 131477

llvm-svn: 131476

llvm-svn: 131475

This is r131438 with a couple small fixes.

llvm-svn: 131474

llvm-svn: 131471

llvm-svn: 131469

passed as the fifth parameter, insure it's passed correctly (in R9).
rdar://problem/6920088

llvm-svn: 131467

The greedy register allocator has live range splitting and register class
inflation, so it can actually fully undo this join, including restoring the
original register classes.

We still don't want to do this for long live ranges, mostly because of the high
register pressure of there are many constrained live ranges overlapping.

llvm-svn: 131466

getHostTriple. This fixes a 32 bit clang running on a 64 bit ubuntu.

llvm-svn: 131463

Fix a bug in PerformEXTRACT_VECTOR_ELTCombine. The code created an ADD SDNode
with two different types, in cases where the index and the ptr had different
types.

llvm-svn: 131461

llvm-svn: 131459

Finishes off rdar://8470697

llvm-svn: 131458

llvm-svn: 131457

llvm-svn: 131456

llvm-svn: 131455

llvm-svn: 131452

it more tomorrow.

llvm-svn: 131451

llvm-svn: 131444

llvm-svn: 131439

llvm-svn: 131438

llvm-svn: 131437

When instructions are deleted, they leave tombstone SlotIndex entries.
The isZeroLength method should ignore these null indexes.

This causes RABasic to sometimes spill a callee-saved register in the
abi-isel.ll test, so don't run that test with -regalloc=basic.  Prioritizing
register allocation according to spill weight can cause more registers to be
used.

llvm-svn: 131436

llvm-svn: 131431

llvm-svn: 131430

llvm-svn: 131429