llvm-svn: 47452

llvm-svn: 47448

llvm-svn: 47437

llvm-svn: 47435

llvm-svn: 47434

llvm-svn: 47433

llvm-svn: 47432

llvm-svn: 47431

Atomic op support.  If any gcc test uses __sync builtins, it might start failing on archs that haven't implemented them yet

llvm-svn: 47430

Eli Friedman.  This implements CodeGen/Generic/2008-02-20-MatchingMem.ll.

llvm-svn: 47428

llvm-svn: 47427

inline asms.

Fix PR2078 by marking aliases of registers used when a register is 
marked used.  This prevents EAX from being allocated when AX is listed
in the clobber set for the asm.

llvm-svn: 47426

llvm-svn: 47425

Now, we have very first multiple return value testcase!

llvm-svn: 47424

llvm-svn: 47422

llvm-svn: 47416

llvm-svn: 47411

llvm-svn: 47409

llvm-svn: 47408

	ret i32 1, i8 2
another step towards multiple return value support.

llvm-svn: 47407

One small step towards multiple return value support.

llvm-svn: 47406

llvm-svn: 47402

llvm-svn: 47401

llvm-svn: 47400

No need to go up more levels. A def of a register also sets its sub-registers
(so if PhysRegInfo[SuperReg] is NULL, it means SuperReg's super registers are
not previously defined).

llvm-svn: 47399

llvm-svn: 47397

llvm-svn: 47396

llvm-svn: 47395

llvm-svn: 47394

consistency.

llvm-svn: 47393

llvm-svn: 47392

llvm-svn: 47391

llvm-svn: 47390

llvm-svn: 47389

llvm-svn: 47388

llvm-svn: 47387

llvm-svn: 47386

llvm-svn: 47385

and splitting extract_subvector.  This fixes nine
"make check" testcases, for example
2008-02-04-ExtractSubvector.ll and (partially)
CodeGen/Generic/vector.ll.

llvm-svn: 47384

llvm-svn: 47383