[AVX] Implement BUILD_VECTOR lowering for 256-bit vectors.  For
anything but the simplest of cases, lower a 256-bit BUILD_VECTOR by
splitting it into 128-bit parts and recombining.

llvm-svn: 125105

If a live range is used by a terminator instruction, and that live range needs
to leave the block on the stack or in a different register, it can be necessary
to have both sides of the split live at the terminator instruction.

Example:

  %vreg2 = COPY %vreg1
  JMP %vreg1

Becomes after spilling %vreg2:

  SPILL %vreg1
  JMP %vreg1

The spill doesn't kill the register as is normally the case.

llvm-svn: 125102

llvm-svn: 125101

I've been using this mode to narrow down llc unit tests. Example
custom compile script:
llc "$@"
not pygrep.py 'mul\s+r([0-9]), r\1,' < bugpoint-test-program.s

llvm-svn: 125096

llvm-svn: 125095

llvm-svn: 125091

llvm-svn: 125090

Avoid using the same register for two def operands or and earlyclobber
def and use operand. This fixes PR8986 and improves on the prior fix
for rdar://problem/8959122.

llvm-svn: 125089

t2LDRpci with t2LDRi12.
There are a couple of problems with this.
1. The encoding for the literal and immediate constant are different.
   Note bit 7 of the literal case is 'U' so it can be negative.
2. t2LDRi12 is now narrowed to tLDRpci before constant island pass is run.
   So we end up never using the Thumb2 instruction, which ends up creating a
   lot more constant islands.

llvm-svn: 125074

the active loop. This is generally desirable, and it avoids trouble
in situations such as the testcase in PR9123, though the failure
mode depends on use-list order, so it is infeasible to test.

llvm-svn: 125065

After uses of a live range are removed, recompute the live range to only cover
the remaining uses. This is necessary after rematerializing the value before
some (but not all) uses.

llvm-svn: 125058

SimplifyCFG: Track the number of used icmps when turning a icmp chain into a switch. If we used only one icmp, don't turn it into a switch.

Also prevent the switch-to-icmp transform from creating identity adds, noticed by Marius Wachtler.

llvm-svn: 125056

llvm-svn: 125055

llvm-svn: 125054

parsing of operands introduced in r125030. As a small note, besides using a more
generic approach we can also have more descriptive output when debugging
llvm-mc, example:

mcr  p7, #1, r5, c1, c1, #4

note: parsed instruction:
  ['mcr', <ARMCC::al>,
          <coprocessor number: 7>,
          1,
          <register 73>,
          <coprocessor register: 1>,
          <coprocessor register: 1>,
          4]
llvm-svn: 125052

llvm-svn: 125047

Motivation: Improve the parsing of not usual (different from registers or
immediates) operand forms.

This commit implements only the generic support. The ARM specific modifications
will come next.

A table like the one below is autogenerated for every instruction
containing a 'ParserMethod' in its AsmOperandClass

static const OperandMatchEntry OperandMatchTable[20] = {
 /* Mnemonic, Operand List Mask, Operand Class, Features */
 { "cdp", 29 /* 0, 2, 3, 4 */, MCK_Coproc, Feature_IsThumb|Feature_HasV6 },
 { "cdp", 58 /* 1, 3, 4, 5 */, MCK_Coproc, Feature_IsARM },

A matcher function very similar (but lot more naive) to
MatchInstructionImpl scans the table. After the mnemonic match, the
features are checked and if the "to be parsed" operand index is
present in the mask, there's a real match. Then, a switch like the one
below dispatch the parsing to the custom method provided in
'ParseMethod':

 case MCK_Coproc:
   return TryParseCoprocessorOperandName(Operands);

llvm-svn: 125030

[AVX] Insert/extract subvector lowering support.  This includes a
couple of utility functions that will be used in other places for more
AVX lowering.

llvm-svn: 125029

llvm-svn: 125025

llvm-svn: 125023

llvm-svn: 125019

The vld1-lane, vld1-dup and vst1-lane instructions do not yet support using
post-increment versions, but all the rest of the NEON load/store instructions
should be handled now.

llvm-svn: 125014

These operations are expanded to pairs of loads or stores, and the first one
uses the address register update to produce the address for the second one.
So far, the second load/store has also updated the address register, just
for convenience, since that output has never been used.  In anticipation of
actually supporting post-increment updates for these operations, this changes
the non-updating operations to use a non-updating load/store for the second
instruction.

llvm-svn: 125013

llvm-svn: 125012

llvm-svn: 125011

until the instructions are emitted or printed.

llvm-svn: 125010

llvm-svn: 125009

Factor some code better.

llvm-svn: 125006

to simplify the "(X/Y)*Y->X when the division is exact" transform.

llvm-svn: 125004

llvm-svn: 125002

Fixes PR9159.

llvm-svn: 125001

failures with relocations.

The code committed is a first cut at compatibility for emitted relocations in
ELF .o.

Why do this? because existing ARM tools like emitting relocs symbols as
explicit relocations, not as section-offset relocs.

Result is that with these changes,
1) relocs are now substantially identical what to gcc outputs.
2) larger apps (including many spec2k tests) compile, cross-link, and pass

Added reminder fixme to tests for future conversion to .s form.

llvm-svn: 124996

Unified EmitTextAttribute for both Asm and Obj emission (.cpu only)
Added necessary cortex-A8 related attrs for codegen compat tests.

llvm-svn: 124995

when the div is an exact udiv.

llvm-svn: 124994

llvm-svn: 124993

instcombine xform to exercise this.

Nothing forms exact udivs yet though.  This is progress on PR8862

llvm-svn: 124992

if we weren't going to inline the function. The rest of the code using
this was removed.

Fixes PR9154.

llvm-svn: 124991

llvm-svn: 124990

llvm-svn: 124989

When loading from a constant, fold inttoptr if the integer type and the resulting pointer type both have the same size.

llvm-svn: 124987