llvm-svn: 142141

llvm-svn: 142122

Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.

llvm-svn: 141065

shuffle before inserting on a 256-bit vector.
- Add AVX versions of movd/movq instructions
- Introduce a few COPY patterns to match insert_subvector instructions.
This turns a trivial insert_subvector instruction into a register copy,
coalescing the xmm into a ymm and avoid emiting on more instruction.

llvm-svn: 136002

Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, use proper aliases for the pclmullqlqdq and friends. PR10269.

llvm-svn: 134424

llvm-svn: 128826

Define most shift masks incrementally to reduce the redundant
hard-coding. Introduce new shift for the VEX flags to replace the
magic constant 32 in various places.

llvm-svn: 128822

in the instruction tables and fixed a few bugs that
were causing decode conflicts.  Rudimentary tests
are coming up in the next patch.

llvm-svn: 127646

Patch by Jai Menon.

llvm-svn: 126165

llvm-svn: 120416

llvm-svn: 120415

it.

llvm-svn: 120412

Use this to make the X86 and ARM targets set isCodeGenOnly=1 
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.

llvm-svn: 117862

else in X86), and add support for pavgusb.  This is apparently the
only instruction (other than movsx) that is preventing ffmpeg from building
with clang.

If someone else is interested in banging out the rest of the 3DNow! 
instructions, it should be quite easy now.

llvm-svn: 115466

What a weird instruction.

llvm-svn: 114190

llvm-svn: 112202

call and jumps.

llvm-svn: 111496

llvm-svn: 111494

llvm-svn: 109248

Add complete assembler support for FMA3 instructions, with descriptions and encodings taken from the AVX manual

llvm-svn: 109204

llvm-svn: 108892

llvm-svn: 108788

Add the x86 VEX_L form to handle special cases where VEX_L must be set.

llvm-svn: 108274

llvm-svn: 108222

in the integrated assembler.  Still some discussion to be
done.

llvm-svn: 107825

Update VEX encoding to support those new instructions

llvm-svn: 107715

- Add AVX SSE2 Move doubleword and quadword instructions.
- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
  in the .td file now have a AVX encoded form already working.

llvm-svn: 107365

Add several AVX MOV flavors
Support VEX encoding for MRMDestReg

llvm-svn: 106912

llvm-svn: 106705

llvm-svn: 106600

llvm-svn: 106588

llvm-svn: 106357

llvm-svn: 106349

be done incrementally and intermixed with the adding of more
AVX instructions. This is a first step in that direction

llvm-svn: 106251

Handle OpSize TSFlag for AVX

llvm-svn: 105869

immediates to avoid breaking the build.

llvm-svn: 105652

In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type

llvm-svn: 105524

yet, only assembly encoding support.

llvm-svn: 105521

llvm-svn: 100466

When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.

This works well because TableGen resolves member references late:

class I : Instruction {
  AddrMode AM = AddrModeNone;
  let TSFlags{3-0} = AM.Value;
}

let AM = AddrMode4 in
def ADD : I;

TSFlags gets the expected bits from AddrMode4 in this example.

llvm-svn: 100384