movw. That is we promote the destination operand to r16. So
        %CH = TRUNC_R16_R8 %BP
is emitted as
        movw %bp, %cx.

This is incorrect. If %cl is live, it would be clobbered.
Ideally we want to do the opposite, that is emitted it as
        movb ??, %ch
But this is not possible since %bp does not have a r8 sub-register.

We are now defining a new register class R16_ which is a subclass of R16
containing only those 16-bit registers that have r8 sub-registers (i.e.
AX - DX). We isel the truncate to two instructions, a MOV16to16_ to copy the
value to the R16_ class, followed by a TRUNC_R16_R8.

Due to bug 770, the register colaescer is not going to coalesce between R16 and
R16_. That will be fixed later so we can eliminate the MOV16to16_. Right now, it
can only be eliminated if we are lucky that source and destination registers are
the same.

llvm-svn: 28164

llvm-svn: 28127

that gets emitted as movl (for r32 to i16, i8) or a movw (for r16 to i8). And
if the destination gets allocated a subregister of the source operand, then
the instruction will not be emitted at all.

llvm-svn: 28119

for now.

Patch contributed by Alexander Friedman.

llvm-svn: 27994

llvm-svn: 27948

x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.

llvm-svn: 27947

- Some bug fixes and naming inconsistency fixes.

llvm-svn: 27377

llvm-svn: 27120

failures from last night

llvm-svn: 26981

llvm-svn: 26966

V8I16, etc.

llvm-svn: 26838

llvm-svn: 26831

- Nuke a bogus comment.

llvm-svn: 26815

llvm-svn: 26604

llvm-svn: 26581

llvm-svn: 26479

* Add patterns to handle GlobalAddress, ConstantPool, etc.
  MOV32ri to materialize these nodes in registers.
  ADD32ri to handle %reg + GA, etc.
  MOV32mi to handle store GA, etc. to memory.

llvm-svn: 26374

  and ExternalSymbol.
- Use C++ code (rather than tblgen'd selection code) to match the above
  mentioned leaf nodes. Do not mutate and nodes and do not record the
  selection in CodeGenMap. These nodes should be safe to duplicate. This is
  a performance win.

llvm-svn: 26335

1. Various asm printer bug.
2. Lowering bug. Now TargetGlobalAddress is wrapped in X86ISD::TGAWrapper.

llvm-svn: 26324

Fixed some existing bugs (wrong predicates, prefixes) at the same time.

llvm-svn: 26310

llvm-svn: 26303

llvm-svn: 26302

llvm-svn: 26301

llvm-svn: 26300

llvm-svn: 26297

llvm-svn: 26296

packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).

llvm-svn: 26294

llvm-svn: 26283

llvm-svn: 26273

and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.

llvm-svn: 26255

llvm-svn: 26244

   proves to be worth 20% on Ptrdist/ks. Might be related to dependency
   breaking support.
2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These
   are used for FR32 / FR64 reg-to-reg copies.
3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to
   spill / restore FsMOVAPSrr and FsMOVAPDrr.

llvm-svn: 26241

llvm-svn: 26234

llvm-svn: 26193

llvm-svn: 26192

printOperand instead.

llvm-svn: 26025

llvm-svn: 25954

flag so it can be flagged to a FST.

llvm-svn: 25953

llvm-svn: 25887

- Added a new format for instructions where the source register is implied
  and it is same as the destination register. Used for pseudo instructions
  that clear the destination register.

llvm-svn: 25872