of the virtual register to certain functions.

llvm-svn: 11143

operand of the instruction and thus simplify the register allocation.

llvm-svn: 11124

spilled, A was loaded from its stack location twice. This fixes the bug.

llvm-svn: 11093

llvm-svn: 11088

much better when I get rid of the reserved registers.

llvm-svn: 11066

registers (not as the max number of registers).

Change toSpill from a std::set into a std::vector<bool>.

Use the reverse iterator adapter to do a reverse scan of allocatable
registers.

llvm-svn: 11061

where appropriate.

llvm-svn: 11060

MRegisterInfo::isVirtualRegister.

llvm-svn: 11045

is a move between two registers, at least one of the registers is
virtual and the two live intervals do not overlap.

This results in about 40% reduction in intervals, 30% decrease in the
register allocators running time and a 20% increase in peephole
optimizations (mainly move eliminations).

The option can be enabled by passing -join-liveintervals where
appropriate.

llvm-svn: 10965

with the current one.

llvm-svn: 10959

virtReg lives on the stack. Now a virtual register has an entry in the
virtual->physical map or the virtual->stack slot map but never in
both.

llvm-svn: 10958

register yet (2nd try).

llvm-svn: 10896

register yet.

llvm-svn: 10895

LiveIntervals::Interval::expiredAt() and simplify regalloc code.

llvm-svn: 10894

llvm-svn: 10834

llvm-svn: 10820

overlap before adding their spill weight.

llvm-svn: 10819

of the register allocator as follows:

       before   after
mesa   2.3790  1.5994
vpr    2.6008  1.2078
gcc    1.9840  0.5273
mcf    0.2569  0.0470
eon    1.8468  1.4359
twolf  0.9475  0.2004
burg   1.6807  1.3300
lambda 1.2191  0.3764

Speedups range anyware from 30% to over 400% :-)

llvm-svn: 10712

llvm-svn: 10711

llvm-svn: 10710

llvm-svn: 10695

saved register it has a longer free range than ECX (which is defined
every time there is a fnuction call) which makes ECX a better register
to reserve.

llvm-svn: 10635

which denotes the register we would like to be assigned to (virtual or
physical). In register allocation, if this hint exists and we can map
it to a physical register (it is either a physical register or it is a
virtual register that already got assigned to a physical one) we use
that register if it is available instead of a random one in the free
pool.

llvm-svn: 10634

llvm-svn: 10604

allocation in the presence of preallocated intervals.

llvm-svn: 10595

llvm-svn: 10570

nesting level when computing it. Right now the allocator uses:

    w = sum_over_defs_uses( 10 ^ nesting level );

llvm-svn: 10569

for live ranges that fall into assigned registers' holes.

llvm-svn: 10566

Add a statistic for # reloads

llvm-svn: 10518

instruction pass. This also fixes all remaining bugs for this new
allocator to pass all tests under test/Programs.

llvm-svn: 10515

are not reserved registers.

llvm-svn: 10514

llvm-svn: 10511

    a) remove opIsUse(), opIsDefOnly(), opIsDefAndUse()
    b) add isUse(), isDef()
    c) rename opHiBits32() to isHiBits32(),
              opLoBits32() to isLoBits32(),
              opHiBits64() to isHiBits64(),
              opLoBits64() to isLoBits64().

This results to much more readable code, for example compare
"op.opIsDef() || op.opIsDefAndUse()" to "op.isDef()" a pattern used
very often in the code.

llvm-svn: 10461

register too.

llvm-svn: 10450

llvm-svn: 10448

llvm-svn: 10447

potential register assignment.

llvm-svn: 10291

llvm-svn: 10288

bug where spill instructions were added to the next basic block
instead of the end of the current one if the instruction that required
the spill was the last in the block.

llvm-svn: 10272

llvm-svn: 10268