go to the same destination. Now we're producing really good code for
switch-lower-feature.ll testcase

llvm-svn: 35672

llvm-svn: 35660

Trivially re-materializable instructions have spill weights that are half of what it would be otherwise.

llvm-svn: 35658

llvm-svn: 35618

2. Help DAGCombiner recognize zero/sign/any-extended versions of ROTR and ROTL
patterns. This was motivated by the X86/rotate.ll testcase, which should now
generate code for other platforms (and soon-to-come platforms.) Rewrote code
slightly to make it easier to read.

llvm-svn: 35605

llvm-svn: 35600

Make sure that the CTPOP result is casted to i32 as the bit counting
intrinsics all return i32 now (this affects CTLZ and CTTZ as well).

llvm-svn: 35567

Support overloaded intrinsics bswap, ctpop, cttz, ctlz.

llvm-svn: 35547

Adjust for changes in the bit counting intrinsics. They all return i32
now so we have to trunc/zext the DAG node accordingly.

llvm-svn: 35546

Change getOperationName to return std::string instead of const char*

llvm-svn: 35545

llvm-svn: 35529

llvm-svn: 35527

llvm-svn: 35522

llvm-svn: 35520

combination.

llvm-svn: 35517

register more than once.

llvm-svn: 35513

of dead def live interval at 1 to avoid multiple def's targeting the same
register. The previous patch missed a case where the source operand is live-in.
In that case, remove the whole interval.

llvm-svn: 35512

big endian targets until llvm-gcc build issue has been resolved.

llvm-svn: 35449

llvm-svn: 35445

llvm-svn: 35420

llvm-svn: 35419

llvm-svn: 35407

llvm-svn: 35406

1) Take address scale into consideration. e.g. i32* -> scale 4.
2) Examine all the users of GEP.
3) Generalize to inter-block GEP's (no longer uses loopinfo).
4) Don't do xform if GEP has other variable index(es).

llvm-svn: 35403

not violate that.

llvm-svn: 35396

llvm-svn: 35380

llvm-svn: 35379

llvm-svn: 35376

TID->numOperands.

llvm-svn: 35375

llvm-svn: 35365

llvm-svn: 35363

hopefully forestall similar errors.

llvm-svn: 35362

llvm-svn: 35350

strategy, emit JT's where possible.

llvm-svn: 35338

CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll

llvm-svn: 35332

implement initial support for the silly X constraint.  Testcase here: CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll

llvm-svn: 35327

llvm-svn: 35324

not just the first letter.  No functionality change.

llvm-svn: 35322

llvm-svn: 35299

llvm-svn: 35293