llvm-svn: 31675

llvm-svn: 31674

produces this clever code:

_millisecs:
        lis r2, ha16(_Time.1182)
        lwzu r3, lo16(_Time.1182)(r2)
        lwz r2, 4(r2)
        addic r4, r2, 1
        addze r3, r3
        blr

instead of this:

_millisecs:
        lis r2, ha16(_Time.1182)
        la r3, lo16(_Time.1182)(r2)
        lwz r2, lo16(_Time.1182)(r2)
        lwz r3, 4(r3)
        addic r4, r3, 1
        addze r3, r2
        blr

for:

long %millisecs() {
        %tmp = load long* %Time.1182            ; <long> [#uses=1]
        %tmp1 = add long %tmp, 1                ; <long> [#uses=1]
        ret long %tmp1
}

llvm-svn: 31673

globals.

llvm-svn: 31672

llvm-svn: 31671

Just add pass into the pass manager queue without processing analysis.

llvm-svn: 31670

required to do so.

llvm-svn: 31669

llvm-svn: 31668

llvm-svn: 31667

llvm-svn: 31666

llvm-svn: 31665

llvm-svn: 31664

pass to explode.  This fixes a bunch of llc-beta failures on ppc last night.

llvm-svn: 31661

llvm-svn: 31660

manager if a pass does not preserve analysis that is used by other
passes.

llvm-svn: 31659

llvm-svn: 31658

llvm-svn: 31656

llvm-svn: 31654

by the shr -> [al]shr patch.  This was reduced from 176.gcc.

llvm-svn: 31653

llvm-svn: 31650

llvm-svn: 31649

take v4f32 / v2f64 operands and may end up causing larger spills / restores.
Added X86 specific nodes X86ISD::FMAX, X86ISD::FMIN instead.

This fixes PR996.

llvm-svn: 31645

CodeGen/Generic/2006-11-10-DAGCombineMiscompile.ll and PPC gsm/toast

llvm-svn: 31644

Inherit CommonPassManagerImpl from Pass.

llvm-svn: 31642

SCALAR_TO_VECTOR, even if the hasOneUse() check pass we may end up folding
the load into two instructions. Make sure we check the SCALAR_TO_VECTOR
has only one use as well.

llvm-svn: 31641

llvm-svn: 31637

llvm-svn: 31634

llvm-svn: 31633

When forming a pre-indexed store, make sure ptr isn't the same or is a pred of value being stored. It would cause a cycle.

llvm-svn: 31631

llvm-svn: 31627

(because the 64-bit reg target versions aren't implemented yet), doesn't
support r+r addr modes, and doesn't handle stores, but it works otherwise. :)

This is disabled unless -enable-ppc-preinc is passed to llc for now.

llvm-svn: 31621

llvm-svn: 31617

Use TargetInstrInfo::getNumOperands() instead of MachineInstr::getNumOperands(). In preparation for implicit reg def/use changes.

llvm-svn: 31616

This should unbreak csretcc on Linux & mingw targets. Several tests from
llvm-test should be also restored (fftbench, bigfib).

llvm-svn: 31613

llvm-svn: 31612

llvm-svn: 31610

llvm-svn: 31608

lazy compilation is ever attempted

llvm-svn: 31602

llvm-svn: 31601

llvm-svn: 31599