llvm-svn: 85653

llvm-svn: 85648

It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming.

llvm-svn: 85643

llvm-svn: 85641

llvm-svn: 85640

llvm-svn: 85639

results. This works around a problem affecting targets which rely on
MVT::Flag to handle physical register defs.

llvm-svn: 85638

llvm-svn: 85637

llvm-svn: 85636

llvm-svn: 85635

PHI operands by the predecessor order, sort them by the order used by the
first PHI in the block. This is still suffucient to expose duplicates.

llvm-svn: 85634

Daniel Dunbar.
- Reordered the fields in the ARMOperand Mem struct to make the struct smaller.
Making bool's into 1 bit fields and put the MCExpr* fields adjacent to each
other.
- Fixed a number of places in ARMAsmParser.cpp so they have doxygen comments.
- Change the name of ARMAsmParser::ParseRegister() to MaybeParseRegister and
added the bool ParseWriteBack parameter.
- Changed ARMAsmParser::ParseMemory() to call MaybeParseRegister().
- Added ARMAsmParser::ParseMemoryOffsetReg to factor out parsing the offset of a
memory operand.  And use it for both parsing both preindexed and post indexing
addressing forms in ARMAsmParser::ParseMemory.
- Changed the first argument to ParseShift() to a reference.
- Changed ParseShift() to check for Rrx first and return to reduce nesting.

llvm-svn: 85632

llvm-svn: 85630

around, then zap them.  This is analogous to dangling constantexprs hanging
off functions.

llvm-svn: 85627

This reduces codesize on a variety of codes by 1-2% on x86-64. It also
helps clean up after SSAUpdater.

llvm-svn: 85626

llvm-svn: 85625

llvm-svn: 85624

This helps expose duplicate PHIs, which will make it easier for them
to be eliminated.

llvm-svn: 85623

unfolding loads for hoisting.  getOpcodeAfterMemoryUnfold returns the
opcode of the original operation without the load, not the load
itself, MachineLICM needs to know the operand index in order to get
the correct register class. Extend getOpcodeAfterMemoryUnfold to
return this information.

llvm-svn: 85622

llvm-svn: 85621

llvm-svn: 85619

llvm-svn: 85615

llvm-svn: 85614

llvm-svn: 85611

llvm-svn: 85610

llvm-svn: 85609

llvm-svn: 85608

apply to the build tools. If we want to allow build tool flags input, we
should have separate inputs (BUILD_CFLAGS and BUILD_CXXFLAGS, perhaps).

llvm-svn: 85607

llvm-svn: 85606

llvm-svn: 85605

llvm-svn: 85599

void f (int a1, int a2, int a3, int a4, int a5,...)

In ARMTargetLowering::LowerFormalArguments if the function has 4 or
more regular arguments we used to set VarArgsFrameIndex using an
offset of 0, which is only correct if the function has exactly 4
regular arguments.

llvm-svn: 85590

llvm-svn: 85587

Rather than having llvm-gcc changing the meaning of OptimizeSize, just make sure loop unswitch is conservative when optimization level is < 3.

llvm-svn: 85581

clang/test/CodeGen/indirect-goto.c runs! (unoptimized)

llvm-svn: 85577

llvm-svn: 85575

llvm-svn: 85572

llvm-svn: 85571

llvm-svn: 85568

llvm-svn: 85562