Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.

llvm-svn: 150878

Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.

Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.

Adds a test to verify that the scheduler is working.

Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.

Patch by Preston Gurd!

llvm-svn: 149558

convert all the rest of the cmovs to the multiclass,
with good results:

 X86InstrCMovSetCC.td |  598 +--------------------------------------------------
 X86InstrCompiler.td  |   61 +++++
 2 files changed, 77 insertions(+), 582 deletions(-)

llvm-svn: 115707

(e.g. CMOVBE16rr instead of CMOVBErr16).

llvm-svn: 115705

21 insertions(+), 53 deletions(-)

Moar change coming before I switch the rest.

llvm-svn: 115697

llvm-svn: 115692

 X86InstrCMovSetCC.td |  200 ++++++---------------------------------------------
 1 file changed, 27 insertions(+), 173 deletions(-)

llvm-svn: 115689

llvm-svn: 115686

llvm-svn: 115601