- Sep 26, 2012
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Michael Liao authored
llvm-svn: 164675
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Michael Liao authored
llvm-svn: 164674
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- Feb 18, 2012
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Jia Liu authored
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
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- Feb 02, 2012
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Andrew Trick authored
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! llvm-svn: 149558
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- Jan 03, 2012
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Devang Patel authored
llvm-svn: 147453
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- Oct 24, 2011
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Craig Topper authored
llvm-svn: 142779
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- Oct 23, 2011
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Craig Topper authored
llvm-svn: 142741
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- Nov 06, 2010
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Chris Lattner authored
shift-by-1 instructions, where the asmstring doesn't contain the implicit 1. It turns out that a bunch of these rotate instructions were completely broken because they used 1 instead of $1. This fixes assembly mismatches on "rclb $1, %bl" and friends, where we used to generate the 3 byte form, we now generate the proper 2-byte form. llvm-svn: 118355
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- Oct 05, 2010
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Chris Lattner authored
llvm-svn: 115608
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Chris Lattner authored
llvm-svn: 115607
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