create symbols.  It is extremely error prone and a source of a lot
of the remaining integrated assembler bugs on x86-64.

This fixes rdar://7807601.

llvm-svn: 99902

to be fixed any time soon.

llvm-svn: 99888

MCContext. There is still one leak left in PIC16Section (the Items vector).

llvm-svn: 99887

llvm-svn: 99859

llvm-svn: 99855

Cross-block inference is primitive and wrong, but the pass is working otherwise.

llvm-svn: 99848

makes calls a little bit more consistent and allows easy removal of the
specializations in the future. Convert all callers to the templated functions.

llvm-svn: 99838

the SDNodes.

llvm-svn: 99835

Most of these were unused, some of them were wrong and unused (isS16Constant<short>,
isS10Constant<short>).

llvm-svn: 99827

"the bigstack patch for SPU, with testcase. It is essentially the patch committed as 97091, and reverted as 97099, but with the following additions:
-in vararg handling, registers are marked to be live, to not confuse the register scavenger
-function prologue and epilogue are not emitted, if the stack size is 16. 16 means it is empty - there is only the register scavenger emergency spill slot, which is not used as there is no stack."

llvm-svn: 99819

llvm-svn: 99815

These instructions use byte index in a control vector (M:Vm) to lookup byte
values in a table and generate a new vector (D:Vd).  The table is specified via
a list of vectors, which can be:

{Dn}
{Dn D<n+1>}
{Dn D<n+1> D<n+2>}
{Dn D<n+1> D<n+2> D<n+3>}

llvm-svn: 99789

llvm-svn: 99770

llvm-svn: 99760

matchable: it seems like it would always constant fold.

llvm-svn: 99758

this also depends on the new "bitconvert dropping" behavior just
added to tblgen.

llvm-svn: 99757

llvm-svn: 99755

input to be v8i8 or v16i8, which buildvectors get canonicalized to.

This allows the patterns that were previously using a bare 'vnot' to
match, before they couldn't.

llvm-svn: 99754

patterns that would never match because of bitcast, and eliminating use
of vnot_conv.

llvm-svn: 99753

llvm-svn: 99750

*input* of other type, which is the VT. 

llvm-svn: 99749

llvm-svn: 99748

llvm-svn: 99743

their flags correctly.

llvm-svn: 99738

llvm-svn: 99737

nodes all have an EFLAGS result when made by isel lowering.

llvm-svn: 99736

llvm-svn: 99705

llvm-svn: 99704

llvm-svn: 99700

it as the format for the appropriate N3V*SL*<> classes.  These instructions
require special handling of the M:Vm field which encodes the restricted Dm and
the lane index within Dm.

Examples are A8.6.325 VMLA, VMLAL, VMLS, VMLSL (by scalar):

	vmlal.s32	q3, d2, d10[0]

llvm-svn: 99690

llvm-svn: 99686

through to the generic version. The generic functions use STR/LDR, but T2
needs the t2STR/t2LDR instead so we get the addressing mode correct.

llvm-svn: 99678

to now take a format argument.  N3VDInt<> and N3VQInt<> are modified to take a
format argument as well.

llvm-svn: 99676

to encode the byte location of the extracted result in the concatenation of the
operands, from the least significant end.

Modify VEXTd and VEXTq classes to use the format.

llvm-svn: 99659

follow the N3RegFrm's operand order of D:Vd N:Vn M:Vm.  The operand order of
N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the first src operand).

Add a parent class N3Vf which requires passing a Format argument and which the
N3V class is modified to inherit from.  N3V class represents the "normal"
3-Register NEON Instructions with N3RegFrm.

Also add a multiclass N3VSh_QHSD to represent clusters of NEON 3-Register Shift
Instructions and replace 8 invocations with it.

llvm-svn: 99655

Radar 7797856

llvm-svn: 99630

Examples are VABA (Vector Absolute Difference and Accumulate), VABAL (Vector
Absolute Difference and Accumulate Long), and VABD (Vector Absolute Difference).

llvm-svn: 99628

llvm-svn: 99620

llvm-svn: 99598

dispatch to the appropriate routines to handle the different interpretations of
the shift amount encoded in the imm6 field.  The Vd, Vm fields are interpreted
the same between the two, though.

See, for example, A8.6.367 VQSHL, VQSHLU (immediate) for N2RegVShLFrm format and
A8.6.368 VQSHRN, VQSHRUN for N2RegVShRFrm format.

llvm-svn: 99590