the ARMExpandPseudos pass rather than during the asm lowering.

llvm-svn: 117714

llvm-svn: 117703

llvm-svn: 117702

llvm-svn: 117695

llvm-svn: 117687

vldr.64 to work.  I have no idea if this is fully right, but 
it is in the right direction.

llvm-svn: 117626

llvm-svn: 117571

llvm-svn: 117531

llvm-svn: 117520

- For now, loads of [r, r] addressing mode is the same as the
  [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
  identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
  is "free".

llvm-svn: 117519

complex load / store addressing mode) when they have higher cost and
when they have more than one use.

llvm-svn: 117509

the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752

llvm-svn: 117505

for specifying fractional bits for fixed point conversions.

llvm-svn: 117501

llvm-svn: 117478

rdar://8477752.

llvm-svn: 117419

llvm-svn: 117418

explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

llvm-svn: 117409

llvm-svn: 117188

llvm-svn: 117165

llvm-svn: 117133

llvm-svn: 117121

definitions.

llvm-svn: 117114

llvm-svn: 117108

llvm-svn: 117080

llvm-svn: 117076

llvm-svn: 117072

setup they require. Use this for ARM/Darwin to rematerialize the base
pointer from the frame pointer when required. rdar://8564268

llvm-svn: 116879

llvm-svn: 116768

llvm-svn: 116612

llvm-svn: 116604

llvm-svn: 116588

llvm-svn: 116566

llvm-svn: 116560

llvm-svn: 116537

and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.

llvm-svn: 116534

pseudonym.

llvm-svn: 116512

llvm-svn: 116498

llvm-svn: 116488

llvm-svn: 116449

llvm-svn: 116447