llvm-svn: 107810

This fixes PR7540.

llvm-svn: 107809

llvm-svn: 107807

a separate DCE pass over MachineInstrs.

llvm-svn: 107804

a bunch of stuff, to allow the target-independent calling convention
logic to be employed.

llvm-svn: 107800

llvm-svn: 107798

position when emitting multiple blocks when executing a custom
inserter.

llvm-svn: 107797

llvm-svn: 107796

llvm-svn: 107795

around everywhere, and also give it an InsertPt member, to enable isel
to operate at an arbitrary position within a block, rather than just
appending to a block.

llvm-svn: 107791

instance, rather than pointers to all of FunctionLoweringInfo's
members.

This eliminates an NDEBUG ABI sensitivity.

llvm-svn: 107789

allow target-specific fast-isel code to make use of it directly.

llvm-svn: 107787

code can do calling-convention queries. This obviates OutputArgReg.

llvm-svn: 107786

llvm-svn: 107785

llvm-svn: 107781

llvm-svn: 107780

llvm-svn: 107778

llvm-svn: 107777

interface needs implementations to be consistent, so any code which
wants to support different semantics must use a different interface.
It's not currently worthwhile to add a new interface for this new
concept.

Document that AliasAnalysis doesn't support cross-function queries.

llvm-svn: 107776

llvm-svn: 107767

builds to "Release".  The default build is unchanged (optimization on,
assertions on), however it is now called Release+Asserts.  The intent
is that future LLVM releases released via llvm.org will be Release builds
in the new sense, i.e. will have assertions disabled (currently they have
assertions enabled, for a more than 20% slowdown).  This will bring them
in line with MacOS releases, which ship with assertions disabled.  It also
means that "Release" now means the same things in make and cmake builds:
cmake already disables assertions for "Release" builds AFAICS.

llvm-svn: 107758

llvm-svn: 107752

llvm-svn: 107750

Now that almost all SSE4.1 AVX instructions are added, move code around to more appropriate sections. No functionality changes

llvm-svn: 107749

llvm-svn: 107747

llvm-svn: 107746

Buildbot breakage.

llvm-svn: 107744

llvm-svn: 107743

they've been tested to work.

llvm-svn: 107742

llvm-svn: 107740

than assuming a target will custom lower them. Targets which do so should
exlicitly mark them as having custom lowerings. PR7454.

llvm-svn: 107734

llvm-svn: 107732

allocated to consecutive registers.

llvm-svn: 107730

print the (%rip) only if the 'a' modifier is present.
PR 7528.

llvm-svn: 107727

INSERT_SUBREG will now only appear in SSA machine instructions.

Fix the handling of partial redefs in ProcessImplicitDefs. This is now relevant
since partial redef COPY instructions appear.

llvm-svn: 107726

This means that an instruction defining an S register will affect the domain of
the parent D register.

llvm-svn: 107725

llvm-svn: 107723

llvm-svn: 107720

llvm-svn: 107717

Update VEX encoding to support those new instructions

llvm-svn: 107715