llvm-svn: 124725

This makes the job of the later optzn passes easier, allowing the vast amount of
icmp transforms to chew on it.

We transform 840 switches in gcc.c, leading to a 16k byte shrink of the resulting
binary on i386-linux.

The testcase from README.txt now compiles into
  decl  %edi
  cmpl  $3, %edi
  sbbl  %eax, %eax
  andl  $1, %eax
  ret

llvm-svn: 124724

llvm-svn: 124722

prefix would be misinterpreted in some cases on 32-bit
x86 platforms.  Thanks to Olivier Meurant for identifying
the bug.

llvm-svn: 124709

the load, then it may be legal to transform the load and store to integer
load and store of the same width.

This is done if the target specified the transformation as profitable. e.g.
On arm, this can transform:
vldr.32 s0, []
vstr.32 s0, []

to

ldr r12, []
str r12, []

rdar://8944252

llvm-svn: 124708

This is completely untested but pretty straightforward, so hopefully I
got it right.

llvm-svn: 124694

Patch by Brian G. Lucas!

llvm-svn: 124679

llvm-svn: 124652

llvm-svn: 124639

llvm-svn: 124611

Fix vector sign extend to put the source and destination types in the
correct places.

llvm-svn: 124601

llvm-svn: 124599

llvm-svn: 124570

Teach DAGCombine to fold fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2) when c1 equals the amount of bits that are truncated off.

This happens all the time when a smul is promoted to a larger type.

On x86-64 we now compile "int test(int x) { return x/10; }" into
  movslq  %edi, %rax
  imulq $1717986919, %rax, %rax
  movq  %rax, %rcx
  shrq  $63, %rcx
  sarq  $34, %rax <- used to be "shrq $32, %rax; sarl $2, %eax"
  addl  %ecx, %eax

This fires 96 times in gcc.c on x86-64.

llvm-svn: 124559

Patch by Jyun-Yan You.

llvm-svn: 124492

llvm-svn: 124458

only .syntax unified is supported.

llvm-svn: 124454

[AVX] Clean up the code to configure target lowering for AVX.  Specify
how to lower more/new operations.  This is a prerequisite for adding
additional AVX lowering.

llvm-svn: 124447

Create override of this method in X86/ARM/MBlaze.

llvm-svn: 124378

if we can store a value. Also, the exclusion is or, not and.

Fixes rdar://8920247.

llvm-svn: 124357

CALL64 marks %xmm* as dead.

llvm-svn: 124354

parser. The parser will always give us a binary representation of the floating
point number.

llvm-svn: 124318

[AVX] Add INSERT_SUBVECTOR and support it on x86.  This provides a
default implementation for x86, going through the stack in a similr
fashion to how the codegen implements BUILD_VECTOR.  Eventually this
will get matched to VINSERTF128 if AVX is available.

llvm-svn: 124307

[AVX] Support EXTRACT_SUBVECTOR on x86.  This provides a default
implementation of EXTRACT_SUBVECTOR for x86, going through the stack
in a similr fashion to how the codegen implements BUILD_VECTOR.
Eventually this will get matched to VEXTRACTF128 if AVX is available.

llvm-svn: 124292

llvm-svn: 124288

llvm-svn: 124273

llvm-svn: 124272

llvm-svn: 124270

llvm-svn: 124268

llvm-svn: 124267

llvm-svn: 124233

appropriately so that it prints out the decimal representation.

llvm-svn: 124230

llvm-svn: 124167

llvm-svn: 124151

llvm-svn: 124102

llvm-svn: 124097

define i32 @foo(i32 %x) nounwind readnone ssp {
entry:
  %tobool = icmp eq i32 %x, 0
  %tmp5 = select i1 %tobool, i32 2, i32 1
  ret i32 %tmp5
}

llvm-svn: 124091

llvm-svn: 124082

llvm-svn: 124079

llvm-svn: 124077