llvm-svn: 89218

llvm-svn: 89214

contents of the block to be duplicated.  Use this for ARM Cortex A8/9 to
be more aggressive tail duplicating indirect branches, since it makes it
much more likely that they will be predicted in the branch target buffer.
Testcase coming soon.

llvm-svn: 89187

This is probably not confined to *just* these two things.

Anyway, the llvm-gcc front-end may look up the structure layout information for
an abstract type. That information will be stored into a table with the FE's
TD. Instruction combine can come along and also ask for information on that
abstract type, but for a separate TD (the one associated with the pass manager).

After the type is refined, the old structure layout information in the pass
manager's TD file is out of date. If a new type is allocated in the same space
as the old-unrefined type, then the structure type information in the pass
manager's TD file will be wrong, but won't know it.

Fix this by making the TD's structure type information an abstract type user.

llvm-svn: 89176

llvm-svn: 89143

alignment imm (in the same way). Fix asmprinting for non-darwin platforms.

llvm-svn: 89137

distinguish between them and the more generic instructions (add, mov, and ldr).

llvm-svn: 89108

llvm-svn: 89081

llvm-svn: 89076

is analyzable so it can be updated. If it's not, be safe and don't move the
block.

llvm-svn: 89022

llvm-svn: 89019

llvm-svn: 89011

0b1110 (ALways).  This is so that the disassembler decoder can distinguish among
BX_RET, BRIND, and BXr9.

llvm-svn: 89000

The large code model is documented at
http://www.x86-64.org/documentation/abi.pdf and says that calls should
assume their target doesn't live within the 32-bit pc-relative offset
that fits in the call instruction.

To do this, we turn off the global-address->target-global-address
conversion in X86TargetLowering::LowerCall(). The first attempt at
this broke the lazy JIT because it can separate the movabs(imm->reg)
from the actual call instruction. The lazy JIT receives the address of
the movabs as a relocation and needs to record the return address from
the call; and then when that call happens, it needs to patch the
movabs with the newly-compiled target. We could thread the call
instruction into the relocation and record the movabs<->call mapping
explicitly, but that seems to require at least as much new
complication in the code generator as this change.

To fix this, we make lazy functions _always_ go through a call
stub. You'd think we'd only have to force lazy calls through a stub on
difficult platforms, but that turns out to break indirect calls
through a function pointer. The right fix for that is to distinguish
between calls and address-of operations on uncompiled functions, but
that's complex enough to leave for someone else to do.

Another attempt at this defined a new CALL64i pseudo-instruction,
which expanded to a 2-instruction sequence in the assembly output and
was special-cased in the X86CodeEmitter's emitInstruction()
function. That broke indirect calls in the same way as above.

This patch also removes a hack forcing Darwin to the small code model.
Without far-call-stubs, the small code model requires things of the
JITMemoryManager that the DefaultJITMemoryManager can't provide.

Thanks to echristo for lots of testing!

llvm-svn: 88984

- Check memoperand alignment instead of checking stack alignment. Most load / store folding instructions are not referencing spill stack slots.
- Mark MOVUPSrm re-materializable.

llvm-svn: 88974

llvm-svn: 88964

llvm-svn: 88961

usage of block sizes and offsets.

llvm-svn: 88935

llvm-svn: 88933

llvm-svn: 88919

Analyze has to be before checking the condition, obviously. Properly construct an iterator for prior.

llvm-svn: 88917

llvm-svn: 88887

- Add a smarter constant pool loading, instead of:

lui $2, %hi($CPI1_0)
addiu $2, $2, %lo($CPI1_0)
lwc1 $f0, 0($2)

Generate:

lui $2, %hi($CPI1_0)
lwc1 $f0, %lo($CPI1_0)($2)

llvm-svn: 88886

conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling

llvm-svn: 88874

llvm-svn: 88873

bug 5438.

llvm-svn: 88855

llvm-svn: 88812

llvm-svn: 88805

llvm-svn: 88802

llvm-svn: 88800

 - This is an initial step towards -march=native support in Clang, and towards
   eliminating host dependencies in the targets. See PR5389.

 - Patch by Roman Divacky!

llvm-svn: 88768

llvm-svn: 88762

llvm-svn: 88761

- If destination is a physical register and it has a subreg index, use the
  sub-register instead.
This fixes PR5423.

llvm-svn: 88745

llvm-svn: 88734

llvm-svn: 88705

Move DebugInfo checks into EmitComments and remove them from
target-specific AsmPrinters.  Not all comments need DebugInfo.

Re-enable the line numbers comment test.

llvm-svn: 88697

llvm-svn: 88682

because the testcase is triggering one more bug.

llvm-svn: 88674

PPC is such a target; make it work.

llvm-svn: 87060