V8I16, etc.

llvm-svn: 26838

cost-modeled as producing a flag.  This fixes the test I just added for neg

llvm-svn: 26835

llvm-svn: 26833

llvm-svn: 26831

llvm-svn: 26824

llvm-svn: 26818

llvm-svn: 26817

ADD32ri8.

llvm-svn: 26816

- Nuke a bogus comment.

llvm-svn: 26815

Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.

llvm-svn: 26814

llvm-svn: 26813

llvm-svn: 26810

more target independant, generate better code, and be less conservative.

llvm-svn: 26809

llvm-svn: 26808

llvm-svn: 26807

llvm-svn: 26806

llvm-svn: 26805

llvm-svn: 26804

scale component of the target addressing mode.

llvm-svn: 26802

5 instructions away.

llvm-svn: 26801

llvm-svn: 26800

llvm-svn: 26797

llvm-svn: 26795

llvm-svn: 26793

llvm-svn: 26789

llvm-svn: 26776

llvm-svn: 26762

llvm-svn: 26758

llvm-svn: 26754

llvm-svn: 26743

llvm-svn: 26742

llvm-svn: 26741

llvm-svn: 26740

llvm-svn: 26737

registers, and update it on entry to each function, then restore it on exit.

This compiles:

void func(vfloat *a, vfloat *b, vfloat *c) {
        *a = *b * *c + *c;
}

to this:

_func:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        lvx v0, 0, r5
        lvx v1, 0, r4
        vmaddfp v0, v1, v0, v0
        stvx v0, 0, r3
        mtspr 256, r2
        blr

GCC produces this (which has additional stack accesses):

_func:
        mfspr r0,256
        stw r0,-4(r1)
        oris r0,r0,0xc000
        mtspr 256,r0
        lvx v0,0,r5
        lvx v1,0,r4
        lwz r12,-4(r1)
        vmaddfp v0,v0,v1,v0
        stvx v0,0,r3
        mtspr 256,r12
        blr

llvm-svn: 26733

llvm-svn: 26729

llvm-svn: 26728

llvm-svn: 26725

llvm-svn: 26722

llvm-svn: 26721