Also, fix predicates.

llvm-svn: 189432

llvm-svn: 188848

llvm-svn: 188845

point registers. We will need this register class later when we add
definitions for instructions mfhc1 and mthc1. Also, remove sub-register indices
sub_fpeven and sub_fpodd and use sub_lo and sub_hi instead.

llvm-svn: 188842

load/store instructions defined. Previously, we were defining load/store
instructions for each pointer size (32 and 64-bit), but now we need just one
definition.

llvm-svn: 188830

llvm-svn: 188020

llvm-svn: 187832

This patch implements parsing of mips FCC register operands. The example instructions have been added to test files.

llvm-svn: 187410

register operands.

llvm-svn: 187242

operands.

llvm-svn: 187238

to have register FCC0 (the first floating point condition code register) in
their Uses/Defs list.

No intended functionality change.

llvm-svn: 187233

No functionality change.

llvm-svn: 186642

 This patch represents Mips utilization of r186388 code that alows asm matcher to emit mnemonics contain '.' characters. This makes asm parser code simpler and more efficient.

llvm-svn: 186397

floating point loads and stores.

No changes in functionality.

llvm-svn: 185399

 This patch introduces RegisterOperand class into Mips FPU instruction definitions and adds dedicated parser methods to MipsAsmParser. It is the first in a series of patches that should fix the problems with parsing Mips FPU instructions and optimize the code in MipsAsmParser.

llvm-svn: 184716

Previously, three instructions were needed:

trunc.w.s $f0, $f2
mfc1 $4, $f0
sw $4, 0($2)

Now we need only two:

trunc.w.s $f0, $f2
swc1 $f0, 0($2)

llvm-svn: 182053

invalid instruction sequence.

Rather than emitting an int-to-FP move instruction and an int-to-FP conversion
instruction during instruction selection, we emit a pseudo instruction which gets
expanded post-RA. Without this change, register allocation can possibly insert a
floating point register move instruction between the two instructions, which is not
valid according to the ISA manual.

mtc1 $f4, $4         # int-to-fp move instruction.
mov.s $f2, $f4       # move contents of $f4 to $f2.
cvt.s.w $f0, $f2     # int-to-fp conversion.

llvm-svn: 182042

llvm-svn: 182036

This option is used when the user wants to avoid emitting double precision FP
loads and stores. Double precision FP loads and stores are expanded to single
precision instructions after register allocation.

llvm-svn: 181718

llvm-svn: 178407

functions. Set AddedComplexity to determine the order in which patterns are
matched.

This simplifies selection of floating point loads/stores.

No functionality change intended.

llvm-svn: 175300

llvm-svn: 173401

register names in the standalone assembler llvm-mc.

Registers such as $A1 can represent either a 32 or
64 bit register based on the instruction using it.
In addition, based on the abi, $T0 can represent different
32 bit registers.


The problem is resolved by the Mips specific AsmParser 
td definitions changing to work together. Many cases of
RegisterClass parameters are now RegisterOperand.


Contributer: Vladimir Medic
llvm-svn: 172284

parameter.

llvm-svn: 170661

No functionality change.

llvm-svn: 170084

No functionality change.

llvm-svn: 170077

No functionality change.

llvm-svn: 170076

No functionality change.

llvm-svn: 170075

No functionality change.

llvm-svn: 170073

No functionality change.

llvm-svn: 170072

No functionality change.

llvm-svn: 170071

No functionality change.

llvm-svn: 170069

and separate encoding information from the rest.

llvm-svn: 170066

MipsInstrFPU.td.
 

llvm-svn: 170061

 

llvm-svn: 170060

 

llvm-svn: 170057

FFR2P_M.
 

llvm-svn: 170055

FFR1_W_M and FFR1P_M. The new instruction definitions have one-to-one
correspondence with the instructions in the ISA manual.
 

llvm-svn: 170053

llvm-svn: 169579

support and use it in place of HasMips32r2Or64.

llvm-svn: 168089