llvm-svn: 32333

llvm-svn: 32331

llvm-svn: 32297

llvm-svn: 32293

llvm-svn: 32291

llvm-svn: 32285

llvm-svn: 32284

is 'unsigned'.

llvm-svn: 32279

llvm-svn: 32277

updating the SP link.

llvm-svn: 32202

llvm-svn: 32091

llvm-svn: 32075

2. Float values need to be promoted to double when they are vararg.

llvm-svn: 32074

llvm-svn: 32073

A initialized global variable cannot be extern weak. However, if a global value's initializer is itself a external weak symbol, emit the weak reference.

llvm-svn: 32069

llvm-svn: 32068

llvm-svn: 32057

llvm-svn: 32034

created intrinsics have the right integer types.  This fixes
PowerPC/2006-11-29-AltivecFPSplat.ll

llvm-svn: 32024

llvm-svn: 32019

llvm-svn: 31970

llvm-svn: 31969

llvm-svn: 31966

of opcode and number of operands.

llvm-svn: 31947

llvm-svn: 31902

llvm-svn: 31884

llvm-svn: 31882

Also, valist should create a pointer RC reg class value, not a GPRC value.

llvm-svn: 31840

llvm-svn: 31839

llvm-svn: 31838

The algorithm it used before wasn't 100% correct, we now use an iterative
expansion model.  This fixes assembler errors when compiling 403.gcc with
tail merging enabled.

Change the way the branch selector works overall: Now, the isel generates
PPC::BCC instructions (as it used to) directly, and these BCC instructions
are emitted to the output or jitted directly if branches don't need
expansion.  Only if branches need expansion are instructions rewritten
and created.  This should make branch select faster, and eliminates the
Bxx instructions from the .td file.

llvm-svn: 31837

issues to the ground.

llvm-svn: 31836

value and CR reg #.  This requires swapping the order of these everywhere
that touches BCC and requires us to write custom matching logic for
PPCcondbranch :(

llvm-svn: 31835

llvm-svn: 31834

llvm-svn: 31833

llvm-svn: 31828

2. Offsets on 64-bit stores are still in bytes.

llvm-svn: 31824

llvm-svn: 31823

llvm-svn: 31805

llvm-svn: 31799