default 32/BE target on sparc hosts, and ppc will continue to be the default
on other hosts.

llvm-svn: 16865

llvm-svn: 16618

Add some comments.

llvm-svn: 16611

to find instrs that have delay slots.

llvm-svn: 16610

llvm-svn: 16595

llvm-svn: 16594

llvm-svn: 16591

something, because the wrong bit patterns get output.

llvm-svn: 16590

llvm-svn: 16586

llvm-svn: 16579

Copy constant-pool entries' addresses into registers before loading out of them,
to avoid errors from the assembler.
Handle loading call args past the 6th one off the stack.
Add IMPLICIT_DEF pseudo-instrs for double and long arguments passed in register
pairs.
Use FpMOVD to copy doubles around instead of the horrible store-load thing we
were doing before.
Handle 'ret double' and 'ret long'.
Fix a bug in handling 'and/or/xor long'.

llvm-svn: 16577

moves, not all ORs.

llvm-svn: 16576

llvm-svn: 16575

llvm-svn: 16574

Call the FPMover pass after register allocation.

llvm-svn: 16573

llvm-svn: 16572

llvm-svn: 16571

of FMOVS instrs.

llvm-svn: 16570

llvm-svn: 16526

llvm-svn: 16518

llvm-svn: 16485

llvm-svn: 16484

llvm-svn: 16483

llvm-svn: 16482

llvm-svn: 16481

would appreciate if others would also look at this to make sure I didn't
botch something obvious

llvm-svn: 16312

llvm-svn: 16267

llvm-svn: 16245

llvm-svn: 16138

llvm-svn: 15971

llvm-svn: 15791

llvm-svn: 15780

llvm-svn: 15774

llvm-svn: 15748

llvm-svn: 15586

llvm-svn: 15583

llvm-svn: 15535

llvm-svn: 15494

check this :)

llvm-svn: 15357

llvm-svn: 15192