isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.

llvm-svn: 41958

llvm-svn: 41953

llvm-svn: 41947

1.
[(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
 (modify EFLAGS)]
This indicates the source pattern expects the instruction would produce 2 values. The first is the result of the addition. The second is an implicit definition in register EFLAGS.
2.
def : Pat<(parallel (addc GR32:$src1, GR32:$src2), (modify EFLAGS)), ()>
Similar to #1 except this is used for def : Pat patterns.

llvm-svn: 41897

Next round of x87 long double stuff.
Getting close now, basically works.

llvm-svn: 41875

llvm-svn: 41873

llvm-svn: 41863

llvm-svn: 41862

access to bits).  Use them in place of float and
double interfaces where appropriate.
First bits of x86 long double constants handling 
(untested, probably does not work).

llvm-svn: 41858

information for EH.

llvm-svn: 41852

init_trampoline.  There is now only one
trampoline intrinsic.

llvm-svn: 41841

llvm-svn: 41840

that global stub instead of doing the ".set" thingy we were doing before.

llvm-svn: 41838

llvm-svn: 41812

llvm-svn: 41810

llvm-svn: 41808

instruction. These are implemented with xor which will modify the conditional
code. They should be rematerialized as move instructions.

llvm-svn: 41802

registers. The scheduler is now responsible for emitting them.

llvm-svn: 41781

llvm-svn: 41776

by flagging the associated instructions as being trivially rematerializable.

llvm-svn: 41775

llvm-svn: 41774

The x86-64 ABI states that objects passed on the stack have
8 byte alignment. Implement that.

llvm-svn: 41768

Patch by Sterling Stein!

llvm-svn: 41758

Use APFloat in UpgradeParser and AsmParser.
Change all references to ConstantFP to use the
APFloat interface rather than double.  Remove
the ConstantFP double interfaces.
Use APFloat functions for constant folding arithmetic
and comparisons.
(There are still way too many places APFloat is
just a wrapper around host float/double, but we're
getting there.)

llvm-svn: 41747

leal    (,%rcx,8), %rcx
It should be
leal    (,%rcx,8), %ecx

llvm-svn: 41735

llvm-svn: 41733

llvm-svn: 41717

llvm-svn: 41711

llvm-svn: 41700

llvm-svn: 41680

llvm-svn: 41645

llvm-svn: 41643

This is mandated table 3.1 at
http://www.x86-64.org/documentation/abi.pdf

llvm-svn: 41642

Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.

llvm-svn: 41632

llvm-svn: 41629

llvm-svn: 41628

Comments added. It now generates V5TE multiply instructions. However, it is still necessary to model PUWLSH bits more clearly.

llvm-svn: 41627

llvm-svn: 41626

llvm-svn: 41625

Added support to fold X86 load / store instructions. This allow rematerialized loads to be folded into their uses.

llvm-svn: 41599