Commits · 9da26b20da9d66cb5d2df265c67c05f59a08557f · Roger Ferrer / llvm-epi-0.8 · GitLab

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Sep 27, 2018
- AMDGPU: Split VOP2Inst into VOP2Inst_e32/e64/sdwa · 9da26b20
  Konstantin Zhuravlyov authored Sep 27, 2018
  9da26b20
- AMDGPU/NFC: Simplify VOP_MAC_F16/F32 · 7d424aae
  Konstantin Zhuravlyov authored Sep 27, 2018
  7d424aae
- [AMDGPU] Fold copy (copy vgpr) · b080adfc
  Stanislav Mekhanoshin authored Sep 27, 2018
  b080adfc
- [X86] Remove BT/BTC/BTR/BTS rr/ri overrides · 2a64d393
  Simon Pilgrim authored Sep 27, 2018
  2a64d393
- [X86][Btver2] (V)MPSADBW instructions take 3uops not 1 · 86c7b07e
  Simon Pilgrim authored Sep 27, 2018
  86c7b07e
- Revert r343192 as an ubsan build is currently failing · 8e5676b1
  Luke Cheeseman authored Sep 27, 2018
  8e5676b1
- [X86][Btver2] BTC/BTR/BTS instructions take 2uops not 1 · dd744f15
  Simon Pilgrim authored Sep 27, 2018
  dd744f15
- [X86] Split BT and BTC/BTR/BTS scheduler classes · 29cf499b
  Simon Pilgrim authored Sep 27, 2018
  29cf499b
- [Sparc] EXPENSIVE_CHECKS now passes all machine verifier errors (PR27461) · 06ccc9d9
  Simon Pilgrim authored Sep 27, 2018
  06ccc9d9
- [AArch64] Refactor immediate details out of add/sub tblgen class (NFCI) · 2721e6f0
  Oliver Stannard authored Sep 27, 2018
  2721e6f0
- [AArch64][v8.5A] Add speculation barriers SSBB and PSSBB · a4f68bf4
  Oliver Stannard authored Sep 27, 2018
  a4f68bf4
- [X86][Btver2] BLSI/BLSMSK/BLSR instructions take 2uops not 1 (same as TZCNT) · c2a88ea6
  Simon Pilgrim authored Sep 27, 2018
  c2a88ea6
- [AArch64][v8.5A] Add Branch Target Identification instructions · a9a5eee1
  Oliver Stannard authored Sep 27, 2018
  a9a5eee1
- [AArch64][v8.5A] Add speculation restriction system registers · 8459d34e
  Oliver Stannard authored Sep 27, 2018
  8459d34e
- [AArch64][v8.5A] Add Armv8.5-A random number instructions · dc837e3f
  Oliver Stannard authored Sep 27, 2018
  dc837e3f
- [AArch64][v8.5A] Add Armv8.5-A "DC CVADP" instruction · 6930b12d
  Oliver Stannard authored Sep 27, 2018
  6930b12d
- [AArch64][v8.5A] Add prediction invalidation instructions to AArch64 · 224428c0
  Oliver Stannard authored Sep 27, 2018
  224428c0
- [ARM][v8.5A] Add speculation barrier to ARM & Thumb instruction sets · 382c935c
  Oliver Stannard authored Sep 27, 2018
  382c935c
- [AArch64][v8.5A] Add speculation barrier to AArch64 instruction set · e481f1d9
  Oliver Stannard authored Sep 27, 2018
  e481f1d9
- [Sparc] Remove the support for builtin setjmp/longjmp · 0c05bdea
  Daniel Cederman authored Sep 27, 2018
  0c05bdea
- [AArch64][v8.5A] Add FRINT[32,64][Z,X] instructions · ddb7d46a
  Oliver Stannard authored Sep 27, 2018
  ddb7d46a
- [Sparc] Add unimp alias · b35d3a27
  Daniel Cederman authored Sep 27, 2018
  b35d3a27
- [Sparc] Add support for the partial write PSR instruction · c1968ba5
  Daniel Cederman authored Sep 27, 2018
  c1968ba5
- [X86][Btver2] TZCNT instructions take 2uops not 1 · 98f503a3
  Simon Pilgrim authored Sep 27, 2018
  98f503a3
- [PowerPC] [NFC] Refactor code for printing register operands · a5909675
  Nemanja Ivanovic authored Sep 27, 2018
  a5909675
- [X86][Btver2] Add uops counter for exegesis reports · 7e4f154e
  Simon Pilgrim authored Sep 27, 2018
  7e4f154e
- Reapply changes reverted in r343114, lldb patch to follow shortly · f6844b30
  Luke Cheeseman authored Sep 27, 2018
  f6844b30
- [AArch64][v8.5A] Add PSTATE manipulation instructions XAFlag and AXFlag · 31af178f
  Oliver Stannard authored Sep 27, 2018
  31af178f
- [mips] Add support MIPS r6 Debian triples · e58c45a6
  Simon Atanasyan authored Sep 27, 2018
  e58c45a6
- llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...) · 0cac726a
  Fangrui Song authored Sep 27, 2018
  0cac726a
- [WebAssembly] Fix MRI.hasOneNonDBGUse assert in WebAssemblyRegStackify pass · b3857e4d
  Yury Delendik authored Sep 26, 2018
  b3857e4d
Sep 26, 2018
- AMDGPU/SI: Change predicate to isCIOnly for 32-bit imm s_buffer_load* patterns · 344475fc
  Tom Stellard authored Sep 26, 2018
  344475fc
- [AArch64] Extend single-operand FP insns to match Arm ARM (NFCI) · 29059374
  Oliver Stannard authored Sep 26, 2018
  29059374
- Revert r343112 as CallFrameString API change has broken lldb builds · 77aaa220
  Luke Cheeseman authored Sep 26, 2018
  77aaa220
- [AArch64] Refactor instructions that write PSTATE (NFCI) · c5d192b6
  Oliver Stannard authored Sep 26, 2018
  c5d192b6
- [AArch64] - Return address signing dwarf support · 03ad8812
  Luke Cheeseman authored Sep 26, 2018
  03ad8812
- [AArch64][AsmParser] Show name of missing feature for system instructions · 89b16049
  Oliver Stannard authored Sep 26, 2018
  89b16049
- Revert r343089 "[AArch64] - Return address signing dwarf support" · 00b88bbc
  Hans Wennborg authored Sep 26, 2018
  00b88bbc
- [ARM/AArch64][v8.5A] Add Armv8.5-A target · 7c3c4baa
  Oliver Stannard authored Sep 26, 2018
  7c3c4baa
- [PowerPC] optimize conditional branch on CRSET/CRUNSET · 20982f09
  Hiroshi Inoue authored Sep 26, 2018
  20982f09