Fix t2Int_eh_sjlj_setjmp. Immediate form of orr is a 32-bit instruction. So it should be 22 bytes instead of 20 bytes long.

llvm-svn: 85965

llvm-svn: 85824

llvm-svn: 85809

It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming.

llvm-svn: 85643

clang/test/CodeGen/indirect-goto.c runs! (unoptimized)

llvm-svn: 85577

bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517

Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space.

llvm-svn: 85184

immediate operands when they will fit into the using instruction.

llvm-svn: 84778

llvm-svn: 84751

llvm-svn: 84009

ld / st pairs, etc.

llvm-svn: 83197

Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.

llvm-svn: 83191

Patch by Sylvere Teissier.

llvm-svn: 83135

instruction. This makes it re-materializable.

Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.

llvm-svn: 82982

This should be better than single load from constpool.

llvm-svn: 82948

llvm-svn: 82893

llvm-svn: 80699

llvm-svn: 80350

several things other than Neon vector lane numbers.  For inline assembly
operands with a "c" print code, check that they really are immediates.

llvm-svn: 79676

llvm-svn: 79436

llvm-svn: 79318

llvm-svn: 78970

llvm-svn: 78918

llvm-svn: 78908

llvm-svn: 78905

llvm-svn: 78904

Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.

llvm-svn: 78827

llvm-svn: 78806

llvm-svn: 78777

llvm-svn: 78717

the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713

llvm-svn: 78701

llvm-svn: 78657

llvm-svn: 78610

llvm-svn: 78550

'no_hash' modifier. Hopefully this will make Daniel happy :)

llvm-svn: 78514

llvm-svn: 78410

It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.

This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.

This fixes PR4659 and PR4682.

llvm-svn: 78361

Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.

llvm-svn: 78321

llvm-svn: 78126