Fixed some existing bugs (wrong predicates, prefixes) at the same time.

llvm-svn: 26310

llvm-svn: 26308

llvm-svn: 26305

llvm-svn: 26303

llvm-svn: 26302

llvm-svn: 26301

llvm-svn: 26300

llvm-svn: 26299

instructions are expensive.

llvm-svn: 26298

llvm-svn: 26297

llvm-svn: 26296

Added generic vector types: VR64 and VR128.

llvm-svn: 26295

packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).

llvm-svn: 26294

llvm-svn: 26292

advantage of fisttpll.

llvm-svn: 26288

that the shift may be more easily folded into other operations.

llvm-svn: 26286

llvm-svn: 26283

llvm-svn: 26281

llvm-svn: 26278

llvm-svn: 26273

llvm-svn: 26272

llvm-svn: 26260

llvm-svn: 26259

and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.

llvm-svn: 26255

llvm-svn: 26253

llvm-svn: 26252

llvm-svn: 26250

llvm-svn: 26249

issue. Need to do more experiments.

llvm-svn: 26247

llvm-svn: 26246

llvm-svn: 26245

llvm-svn: 26244

other small targets that do that can be learned from.  They also have
the added advantage of being tested :)

llvm-svn: 26243

   proves to be worth 20% on Ptrdist/ks. Might be related to dependency
   breaking support.
2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These
   are used for FR32 / FR64 reg-to-reg copies.
3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to
   spill / restore FsMOVAPSrr and FsMOVAPDrr.

llvm-svn: 26241

llvm-svn: 26240

and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.

llvm-svn: 26238

llvm-svn: 26234

distinguish between objects and register names, now we can have stuff
with names like "f84", "in6" etc etc.

this should fix one or two tests

llvm-svn: 26232

We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra
instruction in the loop.  Instead, invert the condition and emit
"Loop: ... br!cond Loop; br Out.

Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering.

llvm-svn: 26231

transfer.

According to the Intel P4 Optimization Manual:

Moves that write a portion of a register can introduce unwanted
dependences. The movsd reg, reg instruction writes only the bottom
64 bits of a register, not to all 128 bits. This introduces a dependence on
the preceding instruction that produces the upper 64 bits (even if those
bits are not longer wanted). The dependence inhibits register renaming,
and thereby reduces parallelism.

Not to mention movaps is shorter than movss.

llvm-svn: 26226