llvm-svn: 183587

On PPC32, [su]div,rem on i64 types are transformed into runtime library
function calls. As a result, they are not allowed in counter-based loops (the
counter-loops verification pass caught this error; this change fixes PR16169).

llvm-svn: 183581

the internals of TargetMachine could change.

No functionality change intended.

llvm-svn: 183572

the internals of TargetMachine could change.

No functionality change intended.

llvm-svn: 183571

llvm-svn: 183570

We weren't computing structure size correctly and we were relying on
the original alloca instruction to compute the offset, which isn't
always reliable.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>
llvm-svn: 183568

the internals of TargetMachine could change.

No functionality change intended.

llvm-svn: 183567

This should simplify the subtarget definitions and make it easier to
add new ones.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>
llvm-svn: 183566

the internals of TargetMachine could change.

No functionality change intended.

llvm-svn: 183565

the internals of TargetMachine could change.

No functionality change intended.

llvm-svn: 183561

Reviewed-by: Vincent Lejeune <vljn@ovi.com>

https://bugs.freedesktop.org/show_bug.cgi?id=64257

llvm-svn: 183560

This is the convention used by the other targets.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>
llvm-svn: 183559

Reviewed-by: Vincent Lejeune <vljn@ovi.com>
llvm-svn: 183558

My recent ARM FastISel patch exposed this bug:
  http://llvm.org/bugs/show_bug.cgi?id=16178
The root cause is that it can't select integer sext/zext pre-ARMv6 and
asserts out.

The current integer sext/zext code doesn't handle other cases gracefully
either, so this patch makes it handle all sext and zext from i1/i8/i16
to i8/i16/i32, with and without ARMv6, both in Thumb and ARM mode. This
should fix the bug as well as make FastISel faster because it bails to
SelectionDAG less often. See fastisel-ext.patch for this.

fastisel-ext-tests.patch changes current tests to always use reg-imm AND
for 8-bit zext instead of UXTB. This simplifies code since it is
supported on ARMv4t and later, and at least on A15 both should perform
exactly the same (both have exec 1 uop 1, type I).

2013-05-31-char-shift-crash.ll is a bitcode version of the above bug
16178 repro.

fast-isel-ext.ll tests all sext/zext combinations that ARM FastISel
should now handle.

Note that my ARM FastISel enabling patch was reverted due to a separate
failure when dealing with MCJIT, I'll fix this second failure and then
turn FastISel on again for non-iOS ARM targets.

I've tested "make check-all" on my x86 box, and "lnt test-suite" on A15
hardware.

llvm-svn: 183551

Found be libstdc's debug mode.

llvm-svn: 183549

llvm-svn: 183541

I am able to compile/assemble/link/run /bin/echo from FreeBSD.

llvm-svn: 183537

As a bonus this reduces the loop from O(n^2) to O(n).

llvm-svn: 183532

llvm-svn: 183528

Avoids unused variable warnings in Release builds.

llvm-svn: 183512

the internals of TargetMachine could change.

No functionality change intended.

llvm-svn: 183494

the internals of TargetMachine could change.

llvm-svn: 183493

the internals of TargetMachine could change.

llvm-svn: 183492

the internals of TargetMachine could change.

llvm-svn: 183491

the internals of TargetMachine could change.

llvm-svn: 183490

the internals of TargetMachine could change.

llvm-svn: 183488

These objects are internal to the TargetMachine object and may change.

llvm-svn: 183485

llvm-svn: 183477

Reapply 183271.

llvm-svn: 183472

Reapply 183270 again (because three is a magic number).

This should now no longer seg fault after r183459.

llvm-svn: 183464

llvm-svn: 183463

llvm-svn: 183458

Breaks linux build bots (I thought the problem was something else).

llvm-svn: 183447

Reapply 183270.

llvm-svn: 183445

Reapply 183269.

llvm-svn: 183441

Reapply 183268.

llvm-svn: 183438

Reapply 183267.

llvm-svn: 183436

Add more InstRW mappings.

Reapply 183266.

llvm-svn: 183435

Reapply 183265.

llvm-svn: 183432

Reapply 183264.

llvm-svn: 183430