llvm-svn: 24867

llvm-svn: 24781

llvm-svn: 24775

llvm-svn: 24768

llvm-svn: 24763

llvm-svn: 24760

llvm-svn: 24759

llvm-svn: 24757

llvm-svn: 24756

llvm-svn: 24755

llvm-svn: 24754

llvm-svn: 24727

* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit
zextload.

llvm-svn: 24726

leaaddr.

llvm-svn: 24724

llvm-svn: 24722

llvm-svn: 24721

llvm-svn: 24717

llvm-svn: 24705

llvm-svn: 24696

llvm-svn: 24695

llvm-svn: 24693

llvm-svn: 24690

llvm-svn: 24689

A few helper fragments for loads. e.g. (i8 (load addr:$src)) -> (loadi8 addr:$src). Only to improve readibility.

llvm-svn: 24688

llvm-svn: 24687

llvm-svn: 24686

llvm-svn: 24685

llvm-svn: 24684

llvm-svn: 24683

  This enables the removal of some explicit type casts.
* Rename immZExt8 to i16ZExt8 as well.

llvm-svn: 24682

llvm-svn: 24681

llvm-svn: 24675

base or index operands being selected.

llvm-svn: 24674

first before the chain.
e.g.
int X;

int foo(int x)
{
  x += X + 37;
  return x;
}

If chain operand is selected first, we would generate:
	movl X, %eax
	movl 4(%esp), %ecx
	leal 37(%ecx,%eax), %eax

rather than
	movl $37, %eax
	addl 4(%esp), %eax
	addl X, %eax

which does not require %ecx. (Due to ADD32rm not matching.)

llvm-svn: 24673

llvm-svn: 24671

llvm-svn: 24670

* Added X86 dec patterns.

llvm-svn: 24654

llvm-svn: 24648

llvm-svn: 24637

false if the match is not profitable. e.g. leal 1(%eax), %eax.
* Added patterns for X86 integer loads and LEA32.

llvm-svn: 24635