A8.6.23 BLX (immediate)

rdar://problem/9212921

llvm-svn: 128644

llvm-svn: 128635

llvm-svn: 128633

- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
  {STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible.
- Move all instructions which use am2offset without a pattern to use
  addrmode2.
- Add a new encoding bit to describe the index mode used and teach
  printAddrMode2Operand to check by the addressing mode which index
  mode to print.
- Testcases

llvm-svn: 128632

This revision introduced a dependency cycle, as nlewycky mentioned by email.

llvm-svn: 128597

Somehow we managed to forget to encode the lane index for a large swathe of NEON instructions.  With this fix, the entire test-suite passes with the Thumb integrated assembler.

llvm-svn: 128587

llvm-svn: 128586

  {STR,LDC}{2}_PRE.
- Fixed the encoding in some places.
- Some of those instructions were using am2offset and now use addrmode2.
Codegen isn't affected, instructions which use SelectAddrMode2Offset were not
touched.
- Teach printAddrMode2Operand to check by the addressing mode which index
mode to print.
- This is a work in progress, more work to come. The idea is to change places
which use am2offset to use addrmode2 instead, as to unify assembly parser.
- Add testcases for assembly parser

llvm-svn: 128585

can be recognized. This fixes <rdar://problem/9183078>.

llvm-svn: 128584

llvm-svn: 128574

PHINode::Create() giving the (known or expected) number of operands.

llvm-svn: 128537

was lowering them to sext / uxt + mul instructions. Unfortunately the
optimization passes may hoist the extensions out of the loop and separate them.
When that happens, the long multiplication instructions can be broken into
several scalar instructions, causing significant performance issue.

Note the vmla and vmls intrinsics are not added back. Frontend will codegen them
as intrinsics vmull* + add / sub. Also note the isel optimizations for catching
mul + sext / zext are not changed either.

First part of rdar://8832507, rdar://9203134

llvm-svn: 128502

<rdar://problem/8875309> and <rdar://problem/9057191>.

llvm-svn: 128492

Check early if this is an unsupported opcode, so that we can avoid needlessly instantiating the base register in some cases.

llvm-svn: 128481

The STC_OPTION and STC2_OPTION instructions should have their coprocessor option enclosed in {}.

rdar://problem/9200661

llvm-svn: 128478

llvm-svn: 128467

llvm-svn: 128461

Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during                                                                                                                                    
isel lowering to fold the zero-extend's and take advantage of no-stall
back to back vmul + vmla:
 vmull q0, d4, d6
 vmlal q0, d5, d6
is faster than
 vaddl q0, d4, d5
 vmovl q1, d6                                                                                                                                                                             
 vmul  q0, q0, q1

This allows us to vmull + vmlal for:
    f = vmull_u8(   vget_high_u8(s), c);
    f = vmlal_u8(f, vget_low_u8(s),  c);

rdar://9197392

llvm-svn: 128444

integrated-as.

llvm-svn: 128431

Add comments to ThumbDisassemblerCore.h for recent change made for t2PLD disassembly.

llvm-svn: 128417

llvm-svn: 128405

llvm-svn: 128338

llvm-svn: 128322

masks to match inversely for the code as is to work. For the example given
we actually want:

bfi r0, r2, #1, #1

not #0, however, given the way the pattern is written it's not possible
at the moment.

Fixes rdar://9177502

llvm-svn: 128320

Also add some test cases.

rdar://problem/9189829

llvm-svn: 128304

DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to RegClass.  Add two test cases.

rdar://problem/9182892

llvm-svn: 128299

t2LDREX/t2STREX instructions.  Add two test cases.

llvm-svn: 128293

llvm-svn: 128286

Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm.  Modify the disassembler to handle that.

rdar://problem/9184053

llvm-svn: 128285

rdar://problem/9186136

llvm-svn: 128283

Add an assertion to linear scan to prevent it from allocating registers outside
the register class.

<rdar://problem/9183021>

llvm-svn: 128254

Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the register classes were changed),
modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1.

llvm-svn: 128252

llvm-svn: 128244

llvm-svn: 128243

llvm-svn: 128241

These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt.  Also add a test case.

llvm-svn: 128240

llvm-svn: 128238

llvm-svn: 128236

Set the encoding bits to {0,?,?,0}, not 0.  Plus delegate the disassembly of ADR to
the more generic ADDri/SUBri instructions, and add a test case for that.

llvm-svn: 128234

The MC asm lexer wasn't honoring a non-default (anything but ';') statement
separator. Fix that, and generalize a bit to support multi-character
statement separators.

llvm-svn: 128227