LEA64_32r, eliminating a bunch of modifier logic stuff on addr modes.

Implement support for printing mbb labels as operands.

llvm-svn: 73817

llvm-svn: 73815

llvm-svn: 73813

llvm-svn: 73811

step is to make tblgen generate something more appropriate for MCInst,
and generate calls to operand translation routines where needed.
This includes a bunch of #if 0 code which will slowly be refactored into
something sensible.

llvm-svn: 73810

on X86.  Not useful yet.

llvm-svn: 73799

llvm-svn: 73792

llvm-svn: 73791

llvm-svn: 73786

llvm-svn: 73784

llvm-svn: 73781

llvm-svn: 73767

llvm-svn: 73761

handle with an SSE2 instruction.

llvm-svn: 73760

llvm-svn: 73759

Patch by Benedict Gaster.

llvm-svn: 73753

llvm-svn: 73749

Latency information for ARM v6. It's rough and not yet hooked up. Right now  we are only using branch latency to determine if-conversion limits.

llvm-svn: 73747

while experimenting.  I'm reasonably sure this is correct, but please 
tell me if these instructions have some strange property which makes this
change unsafe.

llvm-svn: 73746

llvm-svn: 73744

implementation.  The idea is that we want asmprinting to
work by converting MachineInstrs into a new MCInst class,
then the per-instruction asmprinter works on MCInst.  MCInst
and the new asmprinters will not depend on most of the 
llvm code generators.  This allows building diassemblers
that don't link in the whole llvm code generator.  This is
step #1 of many.

llvm-svn: 73743

into DarwinTargetAsmInfo.cpp.  The remaining differences should
be evaluated.  It seems strange that x86/arm has .zerofill but ppc
doesn't, etc.

llvm-svn: 73742

llvm-svn: 73738

llvm-svn: 73737

llvm-svn: 73736

llvm-svn: 73734

On Darwin, ams printer should output a second label before a jump table so the linker knows it's a new atom. But this is only needed if the jump table is put in a separate section from the function body.

llvm-svn: 73720

- Update register allocation hint after coalescing. This is done by the target since the hint is target dependent. This is important for ARM register pair hints.
- Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping.
- More fixes to get ARM load / store double word working.

llvm-svn: 73671

adding a check to catch this case at compile time
instead of quietly generating incorrect code.
That will at least let us identify CBE failures
that are not due to this problem.

llvm-svn: 73668

llvm-svn: 73665

llvm-svn: 73661

Emit switch directive for it. I have no idea whether this is
requirement for Darwin or not.

llvm-svn: 73660

Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.

llvm-svn: 73622

Do not use first actual instruction's location for prologue. The debug wants to skip prologue while setting a breakpoint for the function.

llvm-svn: 73592

and its asmprinter.

llvm-svn: 73573

initialization of all targets (InitializeAllTargets.h) or assembler
printers (InitializeAllAsmPrinters.h). This is a step toward the
elimination of relinked object files, so that we can build normal
archives.

llvm-svn: 73543

llvm-svn: 73536

Dispatch C calling conv. to one of these conventions based on
target triple and subtarget features.

llvm-svn: 73530

(this is the case when we have thumb vararg function with single
callee-saved register, which is handled separately).

llvm-svn: 73529

llvm-svn: 73491