llvm-svn: 120006

llvm-svn: 119990

llvm-svn: 119985

llvm-svn: 119947

when transfering between i64 gprs and mmx regs.

llvm-svn: 119931

llvm-svn: 119904

so don't claim they are.  They are allocated using DAG.getNode, so attempts
to access MemSDNode fields results in reading off the end of the allocated
memory.  This fixes crashes with "llc -debug" due to debug code trying to
print MemSDNode fields for these barrier nodes (since the crashes are not
deterministic, use valgrind to see this).  Add some nasty checking to try
to catch this kind of thing in the future.

llvm-svn: 119901

llvm-svn: 119754

llvm-svn: 119740

  sahf	movl	344(%rdi),%r14d
we used to produce:

t.s:2:1: error: unexpected token in argument list

^

we now produce:
t.s:1:11: error: unexpected token in argument list
sahf	movl	344(%rdi),%r14d
    	    	^

rdar://8581401

llvm-svn: 119676

llvm-svn: 119547

a different pass, the complicated interaction between cmov expansion
and fast isel is no longer a concern.

llvm-svn: 119400

Patch by Louis Zhuang!

llvm-svn: 119394

llvm-svn: 119286

Switch the ARM backend to use 'let' instead of 'set' with this change.

llvm-svn: 119120

nodes to indicate when ha16/lo16 modifiers should be used.  This lets
us pass PowerPC/indirectbr.ll.

The one annoying thing about this patch is that the MCSymbolExpr isn't
expressive enough to represent ha16(label1-label2) which we need on
PowerPC.  I have a terrible hack in the meantime, but this will have
to be revisited at some point.

Last major conversion item left is global variable references.

llvm-svn: 119105

llvm-svn: 119098

First step of huge frame-related refactoring: move emit{Prologue,Epilogue} out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place

llvm-svn: 119097

llvm-svn: 119092

since it is trivial and will be shared between ppc and x86.
This substantially simplifies the X86 backend also.

llvm-svn: 119089

llvm-svn: 119088

llvm-svn: 119049

llvm-svn: 119007

llvm-svn: 119006

 - What was I thinking?????

llvm-svn: 118992

llvm-svn: 118954

from the user of the address, fall back to just using the
address in a register instead of bailing out of fast-isel
altogether.

llvm-svn: 118917

llvm-svn: 118916

llvm-svn: 118903

llvm-svn: 118896

llvm-svn: 118865

a leftover from the removal of isExplicit.

llvm-svn: 118774

llvm-svn: 118445

implementing rdar://8431864

llvm-svn: 118364

different forms of this instruction (movw/movl/movq) which we reported
as being ambiguous.  Since they all do the same thing, gas just picks the
one with the shortest encoding.  Follow its lead here.

This implements rdar://8208615

llvm-svn: 118362

llvm-svn: 118361

llvm-svn: 118358

exposed:

GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)"
even though st(0) is implicit in all other fp stack instructions.

Fortunately, there is an alias for fcomip named "fcompi" and gas does
accept the default argument for the alias (boggle!).

As such, switch the canonical form of this instruction to "pi" instead
of "ip".  This makes the code generator and disassembler generate pi,
avoiding the gas bug.

llvm-svn: 118356

shift-by-1 instructions, where the asmstring doesn't contain
the implicit 1.  It turns out that a bunch of these rotate
instructions were completely broken because they used 1 
instead of $1.

This fixes assembly mismatches on "rclb	$1, %bl" and friends,
where we used to generate the 3 byte form, we now generate the
proper 2-byte form.

llvm-svn: 118355

listed in its asm string, for consistency with the other similar
instructions.

llvm-svn: 118354