llvm-svn: 101241

code.  It used to #include the enhanced disassembly
information for the targets it supported straight
out of lib/Target/{X86,ARM,...} but now it uses a
new interface provided by MCDisassembler, and (so
far) implemented by X86 and ARM.

Also removed hacky #define-controlled initialization
of targets in edis.  If clients only want edis to
initialize a limited set of targets, they can set
--enable-targets on the configure command line.

llvm-svn: 101179

llvm-svn: 100754

I also added a rule to the ARM target's Makefile to
build the ARM-specific instruction information table
for the enhanced disassembler.

I will add the test harness for all this stuff in
a separate commit.

llvm-svn: 100735

to a vector that CGT stores instead of synthesizing it on every 
call.

llvm-svn: 98910

llvm-svn: 98468

backend to not use exceptions at all except in cases
of actual error.

llvm-svn: 95762

Disassembler to take advantage of the refactored
AsmWriterInst.h.  Note removed parser code.

llvm-svn: 95760

implementation.  Also changed the constructor
so that it does not require a Record, making it
usable by the EDEmitter.

llvm-svn: 95715

disassembly information have a better comment (and
better guard macros).

llvm-svn: 94781

enhanced disassembler, and the necessary makefile
rules to build the table for X86.

llvm-svn: 94764