llvm-svn: 116370

Turn some fp stackifier assertion into errors to avoid silently generating bad code when assertions are off. rdar://8540457.

llvm-svn: 116368

explicit handling of the instructions referencing it from the MC code
emitter.

llvm-svn: 116367

llvm-svn: 116365

to add 10+ lines to every instruction.

It may turn out that we can move this base class into it's parent class.

llvm-svn: 116362

instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.

llvm-svn: 116360

Fear not! I'm going to try a refactoring right now. :)

llvm-svn: 116359

llvm-svn: 116354

operand values. This is useful for operands which require additional trickery
to encode into the instruction. For example, the ARM shifted immediate and
shifted register operands.

llvm-svn: 116353

llvm-svn: 116348

a separate bit in the coding.

llvm-svn: 116347

llvm-svn: 116339

llvm-svn: 116338

perform initialization without static constructors AND without explicit initialization
by the client.  For the moment, passes are required to initialize both their
(potential) dependencies and any passes they preserve.  I hope to be able to relax
the latter requirement in the future.

llvm-svn: 116334

that says what why what we just asserted is wrong.

llvm-svn: 116333

llvm-svn: 116330

llvm-svn: 116323

llvm-svn: 116322

llvm-svn: 116321

llvm-svn: 116319

llvm-svn: 116318

The reg-reg copies were no longer being generated since copyPhysReg copies
physical registers only.

The loads and stores are not necessary - The TC constraint is imposed by the
TAILJMP and TCRETURN instructions, there should be no need for constrained loads
and stores.

llvm-svn: 116314

ARM instructions.

llvm-svn: 116313

"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers.  Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!

llvm-svn: 116310

address that we've looked through.

Fixes compilation problems in tramp3d from earlier patch.

llvm-svn: 116296

Made necessary edits to configure.ac and regenerated.

llvm-svn: 116291

llvm-svn: 116284

llvm-svn: 116282

llvm-svn: 116280

llvm-svn: 116279

llvm-svn: 116278

llvm-svn: 116277

llvm-svn: 116276

Disable warning C4267 for MSVC. Otherwise it generate literally thousands of warnings when targeting x64. The warning occurs because int is 32 bit but size_t is 64 bit on Win64.

llvm-svn: 116274

llvm-svn: 116272

llvm-svn: 116266

llvm-svn: 116264

stop searching when it has found a match.

llvm-svn: 116262

register operand.

llvm-svn: 116259

Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)

llvm-svn: 116257