Allow target to place 2-address pass inserted copies in better spots. Thumb2 will use this to try to avoid breaking up IT blocks.

llvm-svn: 105745

   %reg1025 = <sext> %reg1024
    ...
   %reg1026 = SUBREG_TO_REG 0, %reg1024, 4

into this:

   %reg1025 = <sext> %reg1024
    ...
   %reg1027 = EXTRACT_SUBREG %reg1025, 4
   %reg1026 = SUBREG_TO_REG 0, %reg1027, 4

The problem here is that SUBREG_TO_REG is there to assert that an implicit zext
occurs. It doesn't insert a zext instruction. If we allow the EXTRACT_SUBREG
here, it will give us the value after the <sext>, not the original value of
%reg1024 before <sext>.

llvm-svn: 105741

llvm-svn: 105740

  is used to assert that an *implicit* zext is performed.

- Fix grammar-o in INSERT_SUBREG. (required reformatting)

llvm-svn: 105735

This will be used primarily by NEON shift intrinsics.

llvm-svn: 105733

green. Dan, please revert this once the real problem is fixed.

llvm-svn: 105732

refer to the "external node" instead.

llvm-svn: 105731

callgraph SCC's.  This makes it match what the node itself would print.  Also,
"indirect callgraph node" doesn't make sense - it has nothing particularly to
do with indirect calls.

llvm-svn: 105730

llvm-svn: 105726

Pulled CodeMetrics out of InlineCost.h and made it a bit more general, so it can be reused from PartialSpecializationCost

llvm-svn: 105725

We default to inserting to lane 0.

llvm-svn: 105722

random load/store, rather than crashing llc.

llvm-svn: 105710

Parenthesize macro args

llvm-svn: 105682

llvm-svn: 105677

'class llvm::DAGDeltaAlgorithm' has virtual functions and accessible non-virtual destructor

Not sure if this is the best solution, but this class has state and some of the
classes that inherit from it also do, so it looks appropriate.

llvm-svn: 105675

llvm-svn: 105674

the same condition, it's important to make sure they are scheduled together
to avoid forming multiple IT blocks. I'm adding a pre-regalloc pass that forms
IT blocks early (by re-scheduling instructions and split basic blocks) to
attempt to fix this. This is not turned on by default since I am not sure this
is the right fix.

Another issue is llvm selects are modeled as two-address conditional moves.
This can be very bad when the copies before the conditional moves are not
coalesced away. Teach IT formation pass to move the copies above the IT block
(when legal) to avoid breaking the IT block.

llvm-svn: 105669

Handle extract hi/lo with common code

llvm-svn: 105666

llvm-svn: 105665

instruction.  Added the 64-bit version "jrcxz" so it is recognized and also
added the checks for incorrect uses of "jcxz" in 64-bit mode and "jrcxz" in
32-bit mode.  Still to do is to correctly handle the encoding of the
instruction adding the Address-size override prefix byte, 0x67, when the width
of the count register is not the same as the mode the machine is running in.
Which for example means the encoding of "jecxz" depends if you are assembling
as a 32-bit target or a 64-bit target.

llvm-svn: 105661

that rip-relative address when executing in 32-bit mode.

llvm-svn: 105656

llvm-svn: 105653

immediates to avoid breaking the build.

llvm-svn: 105652

the register.  While we're at it, make sure it's in the right one.

llvm-svn: 105645

they are out of date, instead of only testing if they exist.

llvm-svn: 105636

llvm-svn: 105634

llvm-svn: 105620

DeltaAlgorithm: Tweak split to split by first/second half instead of even/odd, since adjacent changes are more likely to be related.

llvm-svn: 105613

ADT: Add DAGDeltaAlgorithm, which is a DAG minimization algorithm built on top of the standard 'delta debugging' algorithm.
 - This can give substantial speedups in the delta process for inputs we can construct dependency information for.

llvm-svn: 105612

the llvm tests :-(
It was failing with

-- Testing: 5324 tests, 8 threads --
Fatal Python error: PyEval_AcquireThread: NULL new thread state

llvm-svn: 105610

realloc implementation can try to expand the allocated memory block in-place,
avoiding the copy.

llvm-svn: 105605

Discussed here:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2010-June/032107.html

llvm-svn: 105601

llvm-svn: 105600

Refine BuiltinsARM.def types a bit, we should do a better job of this to save some c++ code in CGBuiltins.

llvm-svn: 105598

llvm-svn: 105591

fix vcvt naming
handle vdup, vcombine with generic vector code

llvm-svn: 105588

- change isShuffleMaskLegal to show that all shuffles with 32-bit and 64-bit
  elements are legal
- the Neon shuffle instructions do not support 64-bit elements, but we were
  not checking for that before lowering shuffles to use them
- remove some 64-bit element vduplane patterns that are no longer needed

llvm-svn: 105586

that it is an immediate before checking that the instruction is an
EXTRACT_SUBREG.

llvm-svn: 105585

llvm-svn: 105561

llvm-svn: 105559