By overriding Pass::verifyAnalysis(), the pass contents will be verified
by the pass manager.

llvm-svn: 160994

Consider address spaces for hashing and CSEing DAG nodes.  Otherwise two loads from different x86 segments but the same address would get CSEd

llvm-svn: 160987

llvm-svn: 160981

where the other_half of the movt and movw relocation entries needs to get set
and only with the 16 bits of the other half.

rdar://10038370

llvm-svn: 160978

This is a cleaned up version of the isFree() function in
MachineTraceMetrics.cpp.

Transient instructions are very unlikely to produce any code in the
final output. Either because they get eliminated by RegisterCoalescing,
or because they are pseudo-instructions like labels and debug values.

llvm-svn: 160977

This function verifies the consistency of cached data in the
MachineTraceMetrics analysis.

llvm-svn: 160976

The MachineTraceMetrics analysis must be invalidated before modifying
the CFG. This will catch some of the violations of that rule.

llvm-svn: 160969

A->isPredecessor(B) is the same as B->isSuccessor(A), but it can
tolerate a B that is null or dangling. This shouldn't happen normally,
but it it useful for verification code.

llvm-svn: 160968

Together with Ran Chachick <ran.chachick@intel.com>

llvm-svn: 160954

llvm-svn: 160953

Mark MOVZX32_NOREX as isCodeGenOnly and neverHasSideEffects. The isCodeGenOnly change allows special detection of _NOREX instructions to be removed from tablegen disassembler code.

llvm-svn: 160951

llvm-svn: 160950

Remove check for sub class of X86Inst from filter function since caller guaranteed it. Replace another sub class check with ShouldBeEmitted flag since it was factored in there already.

llvm-svn: 160949

llvm-svn: 160948

Remove check for f256mem from has256BitOperands as nothing depended on it and it isn't the only 256-bit memory type anyway.

llvm-svn: 160946

llvm-svn: 160945

llvm-svn: 160942

llvm-svn: 160941

Fix up patterns for VCVTSS2SD. Specifically give it priority over SSE form. Add an OptForSpeed to explicitly pair up with an OptForSize that was already on another pattern.

llvm-svn: 160939

llvm-svn: 160938

llvm-svn: 160937

No functionality change.

llvm-svn: 160929

llvm-svn: 160927

llvm-svn: 160925

llvm-svn: 160922

llvm-svn: 160921

Trying to fix the bot by specifying a triple in the failing testing cases.

llvm-svn: 160920

Machine CSE and other optimizations can remove instructions so folding
is possible at peephole while not possible at ISel.

rdar://10554090 and rdar://11873276

llvm-svn: 160919

llvm-svn: 160914

llvm-svn: 160913

It is possible that an instruction can use and update EFLAGS.
When checking the safety, we should check the usage of EFLAGS first before
declaring it is safe to optimize due to the update.

llvm-svn: 160912

Jakob fixed ProcessImplicifDefs in r159149.

llvm-svn: 160910

llvm-svn: 160905

This makes it possible to quickly detect blocks that are outside the
trace.

llvm-svn: 160904

all tests accordingly.

Fixes PR13351.

Patch by shinichiro hamaji!

llvm-svn: 160899

llvm-svn: 160898

llvm-svn: 160897

into predecessor blocks to enable tail call optimization.

rdar://11958338

llvm-svn: 160894

A value number is a PHI def if and only if it begins at a block
boundary. This can be derived from the def slot, a separate flag is not
necessary.

llvm-svn: 160893

This option replaces the existing live interval computation with one
based on LiveRangeCalc.cpp. The new algorithm does not depend on
LiveVariables, and it can be run at any time, before or after leaving
SSA form.

llvm-svn: 160892