llvm-svn: 57715

have an unreachable block in a function. This was triggering the assert. This is
a horrid hack to cover this up.

Oh! for a good debug info architecture!

llvm-svn: 57714

touches memory and need an associated MemOperand

llvm-svn: 57712

ISD condition opcodes into helper functions.

llvm-svn: 57710

llvm-svn: 57709

in 32-bit mode instead of assigning a register pair.  This has nothing to
do with PR2356, but I happened to notice it while working on it.

llvm-svn: 57704

that have different sizes (e.g. i32 and i64) make sure to reserve registers for
the bigger operand.

llvm-svn: 57699

llvm-svn: 57695

other than why it was xfailed.

llvm-svn: 57694

Fix lfence and mfence encoding. These look like MRM5r and MRM6r instructions except they do not have any operands. The RegModRM byte is encoded with register number 0.

llvm-svn: 57692

llvm-svn: 57691

llvm-svn: 57690

constraint.  Reject asms where an output has multiple
input constraints tied to it.

llvm-svn: 57687

array.  Improve some minor comments, refactor some helpers in
AsmOperandInfo.  No functionality change for valid code.

llvm-svn: 57686

llvm-svn: 57677

distinguished from normal (untagged) ones
as per review comment.

I am sufficiently unaquainted with doxygen to
defer the markup to someone with more experience.

llvm-svn: 57676

llvm-svn: 57673

should work for intel long double, but ppc long double aborts
in convert.

llvm-svn: 57672

constants that don't fit in an int. This fixes
"this decimal constant is unsigned only in ISO C90"
warnings.

llvm-svn: 57668

use a SUB instruction instead of an ADD, because -128 can be
encoded in an 8-bit signed immediate field, while +128 can't be.
This avoids the need for a 32-bit immediate field in this case.

A similar optimization applies to 64-bit adds with 0x80000000,
with the 32-bit signed immediate field.

To support this, teach tablegen how to handle 64-bit constants.

llvm-svn: 57663

shift counts, and patterns that match dynamic shift counts
when the subtract is obscured by a truncate node.

Add DAGCombiner support for recognizing rotate patterns
when the shift counts are defined by truncate nodes.

Fix and simplify the code for commuting shld and shrd
instructions to work even when the given instruction doesn't
have a parent, and when the caller needs a new instruction.

These changes allow LLVM to use the shld, shrd, rol, and ror
instructions on x86 to replace equivalent code using two
shifts and an or in many more cases.

llvm-svn: 57662

llvm-svn: 57660

llvm-svn: 57653

llvm-svn: 57649

llvm-svn: 57644

using the 'volatile' qualifier. This should not have any operational consequences
on code, because tags should always be stripped off (giving a non-volatile pointer)
before dereferencing. The new qualification is there to catch some attempts to use
tagged pointers in a context where an untagged pointer is appropriate.

Notably this approach does not catch dereferencing of tagged pointers, but helps
in separating the two concepts a bit.

llvm-svn: 57641

llvm-svn: 57636

uninitialized in these functions with gcc-4.3.

llvm-svn: 57635

warning on x86-64 with gcc-4.3.

llvm-svn: 57634

llvm-svn: 57633

llvm-svn: 57631

x86 backend.  These will all be answered with "patches welcome", so
a PR doesn't help drive them along.

llvm-svn: 57630

basically working, feel free to remove the tag.  The other targets have
really basic things that break them.

llvm-svn: 57628

llvm-svn: 57626

llvm-svn: 57625

llvm-svn: 57622

llvm-svn: 57621

additional information in Loads, Stores, Calls, Invokes,
InsertValueInsts, and ExtractValueInsts.

llvm-svn: 57620

llvm-svn: 57619

llvm-svn: 57618