PR4841.  Patch by Craig Smith!

llvm-svn: 98496

llvm-svn: 98494

MachineInstr -> MCInst.  This is what the assembler backend wants,
it relaxes from smaller to larger things.  This fixes rdar://7750815

llvm-svn: 98493

to get unique assembler temporary labels.

llvm-svn: 98489

contain an MCSymbol instead of a label index.

llvm-svn: 98482

with an MCSymbol instead of an immediate.

llvm-svn: 98481

llvm-svn: 98474

Do not force indirect tailcall through fixed registers: eax, r11. Add support to allow loads to be folded to tail call instructions.

llvm-svn: 98465

an MCSymbol.  Make the EH_LABEL MachineInstr hold its label
with an MCSymbol instead of ID.  Fix a bug in MMI.cpp which
would return labels named "Label4" instead of "label4".

llvm-svn: 98463

instead of label ID's.  This cleans up and regularizes a bunch 
of code and makes way for future progress.

Unfortunately, this pointed out to me that JITDwarfEmitter.cpp
is largely copy and paste from DwarfException/MachineModuleInfo
and other places.  This is very sad and disturbing. :(

One major change here is that TidyLandingPads moved from being
called in DwarfException::BeginFunction to being called in
DwarfException::EndFunction.  There should not be any 
functionality change from doing this, but I'm not an EH expert.

llvm-svn: 98459

llvm-svn: 98458

llvm-svn: 98457

llvm-svn: 98451

and passing off ownership to AsmPrinter.  Now MachineModuleInfo
creates it and owns it by value.  This allows us to use MCSymbols
more consistently throughout the rest of the code generator, and
simplifies a bit of code.  This also allows MachineFunction to 
keep an MCContext reference handy, and cleans up the TargetRegistry
interfaces for AsmPrinters.

llvm-svn: 98450

llvm-svn: 98444

llvm-svn: 98443

llvm-svn: 98431

llvm-svn: 98430

base register updating load/store-multiple instructions.

llvm-svn: 98427

targets.  This is a temporary hack for the .o file writer that Daniel
wants :)

llvm-svn: 98413

writebacks to the address register.  This gets rid of the hack that the
first register on the list was the magic writeback register operand.  There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand.  The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other.  This also fixes Radar 7495976 and should help the verifier work
better for ARM code.

There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.

llvm-svn: 98409

other functionality on 403.gcc compiled at -O0.

llvm-svn: 98405

mostly the same.

llvm-svn: 98402

llvm-svn: 98398

llvm-svn: 98395

llvm-svn: 98394

llvm-svn: 98391

remove it.

llvm-svn: 98390

some of its callers.

llvm-svn: 98388

it to be non-virtual and soon disappear.

llvm-svn: 98387

llvm-svn: 98386

llvm-svn: 98384

llvm-svn: 98380

llvm-svn: 98378

llvm-svn: 98377

actually X86_StdCall or X86_FastCall.

llvm-svn: 98374

llvm-svn: 98373

llvm-svn: 98372

llvm-svn: 98370

llvm-svn: 98369