llvm-svn: 78085

Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations.

llvm-svn: 78081

llvm-svn: 78060

llvm-svn: 78059

llvm-svn: 78057

Remove ARM specific getInlineAsmLength. We'll rely on the simpler (and faster) generic algorithm for now. If more accurate computation is needed, we'll rely on the disassembler.

llvm-svn: 78032

llvm-svn: 78031

Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction.

llvm-svn: 78030

results to fixed registers.

llvm-svn: 78025

llvm-svn: 78024

replicating the logic manually.

llvm-svn: 78011

textual sections.

llvm-svn: 78007

Add a testcase.

llvm-svn: 77992

llvm_report_error already prints "LLVM ERROR:". So stop reporting errors like "LLVM ERROR: llvm: error:" or "LLVM ERROR: ERROR:".

llvm-svn: 77971

llvm-svn: 77949

Use the i12 variant of load / store opcodes if offset is zero. Now we pass all of multisource as well.

llvm-svn: 77939

 - The C, C++, MSIL, and Mips backends still need the module.

llvm-svn: 77927

Module*.

Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.

llvm-svn: 77918

TLOF, unifying all the dwarf targets at the same time.

llvm-svn: 77889

llvm-svn: 77878

the only real caller (GetFunctionSizeInBytes) uses it.

The custom ARM implementation of this is basically reimplementing
an assembler poorly for negligible gain.  It should be removed 
IMNSHO, but I'll leave that to ARMish folks to decide.

llvm-svn: 77877

llvm-svn: 77873

defaults to being ELF.

llvm-svn: 77866

no longer depends on TM!

llvm-svn: 77863

TAI.

llvm-svn: 77842

llvm-svn: 77820

llvm-svn: 77781

llvm-svn: 77764

instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.

Also, we should be using BLX to call external function stubs.

llvm-svn: 77756

llvm-svn: 77744

llvm-svn: 77743

MCSection subclasses yet, but this is a step in the right direction.

llvm-svn: 77708

to ensure the instruction that follows a TBB (when the number of table entries
is odd) is 2-byte aligned.
Patch by Sandeep Patel.

llvm-svn: 77705

  is scaled by two.
- Teach GetInstSizeInBytes about TBB and TBH.

llvm-svn: 77701

initialize method, which can be called when an MCContext is available.

llvm-svn: 77687

When fp is not eliminated, instructions with T2_i12 modes will be changed to T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot.

llvm-svn: 77642

llvm-svn: 77632

llvm-svn: 77627

llvm-svn: 77625

llvm-svn: 77622