llvm-svn: 61513

  instruction sequence and cannot ordinarily be simplified by DAGcombine
  into the various target description files or SPUDAGToDAGISel.cpp.

  This makes some 64-bit operations legal.

- Eliminate target-dependent ISD enums.

- Update tests.

llvm-svn: 61508

Darwin doesn't. Make this optional for platforms.

llvm-svn: 61484

(quad) on a 64-bit platform. This fixes a problem with EH frames on Darwin.

llvm-svn: 61483

non-recursive.

llvm-svn: 61479

and select instructions doesn't buy anything here
except extra complexity: the only difference in
the entire testsuite was that a readonly function
became readnone in MiBench/consumer-typeset.  Add
a comment about this.

llvm-svn: 61478

llvm-svn: 61477

constants, since doing so is irrelevant for aliasing
purposes.  While this doesn't increase the total number
of functions marked readonly or readnone in MultiSource/
Applications (3089), it does result in 12 functions being
marked readnone rather than readonly.
Before:
  readnone: 820
  readonly: 2269
After:
  readnone: 832
  readonly: 2257

llvm-svn: 61469

llvm-svn: 61465

- Move v4i32, i32 mul into SPUInstrInfo.td, with a few more instruction
  cleanups there as well.
- Make SMUL_LOHI, UMUL_LOHI competely illegal for Cell SPU, to better
  assist Chris to see the problem in bug 3101.

llvm-svn: 61464

llvm-svn: 61463

notably, they should support vectors and aggregates.

llvm-svn: 61462

verifier, asm parser, etc can share it.

llvm-svn: 61461

llvm-svn: 61460

Add prototype code for recomputing a live interval's ranges and valnos through recursive phi construction.

llvm-svn: 61458

parameters are pointers.

llvm-svn: 61451

  DAGcombine's ability to find reasons to remove truncates when they were not
  needed. Consequently, the CellSPU backend would produce correct, but _really
  slow and horrible_, code.

  Replaced with instruction sequences that do the equivalent truncation in
  SPUInstrInfo.td.

- Re-examine how unaligned loads and stores work. Generated unaligned
  load code has been tested on the CellSPU hardware; see the i32operations.c
  and i64operations.c in CodeGen/CellSPU/useful-harnesses.  (While they may be
  toy test code, it does prove that some real world code does compile
  correctly.)

- Fix truncating stores in bug 3193 (note: unpack_df.ll will still make llc
  fault because i64 ult is not yet implemented.)

- Added i64 eq and neq for setcc and select/setcc; started new instruction
  information file for them in SPU64InstrInfo.td. Additional i64 operations
  should be added to this file and not to SPUInstrInfo.td.

llvm-svn: 61447

llvm-svn: 61426

llvm-svn: 61425

llvm-svn: 61424

llvm-svn: 61423

llvm-svn: 61420

about other platforms.

llvm-svn: 61415

a symbolic constant. This is unlikely to be intentional, but it
shouldn't crash the compiler.

llvm-svn: 61408

llvm-svn: 61407

llvm-svn: 61405

llvm-svn: 61404

llvm-svn: 61403

other SPEC breakage.  I'll be reverting all recent
changes shortly, this checking is mostly so this
change doesn't get lost.

llvm-svn: 61402

llvm-svn: 61401

llvm-svn: 61400

llvm-svn: 61398

llvm-svn: 61397

llvm-svn: 61396

llvm-svn: 61395

llvm-svn: 61392

Silence unused variable warning.

llvm-svn: 61391

llvm-svn: 61390

This removes all the _8, _16, _32, and _64 opcodes and replaces each
group with an unsuffixed opcode. The MemoryVT field of the AtomicSDNode
is now used to carry the size information. In tablegen, the size-specific
opcodes are replaced by size-independent opcodes that utilize the
ability to compose them with predicates.

This shrinks the per-opcode tables and makes the code that handles
atomics much more concise.

llvm-svn: 61389

llvm-svn: 61385