Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions.

llvm-svn: 192567

Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding.

llvm-svn: 192566

Mark MOVMSKPS/MOVMSKPD/VPINSRWrr64i as AsmParserOnly to remove them from the disassembler tables. Add PINSRWrr64i to complement the AVX version.

llvm-svn: 192565

llvm-svn: 192564

Don't use 64-bit versions of MOVMSKPD in CodeGen. The instructions only produce a 1-bit result so we can just use SUBREG_TO_REG to extend the 32-bit versions.

llvm-svn: 192562

We don't delay load it so it shouldn't be going anywhere.

llvm-svn: 192561

This can happen when processing command line arguments, which
are often stored as std::string's and later turned into
StringRef's via std::string::data().  Unfortunately this
is not guaranteed to return a null-terminated string
until C++11, causing breakage on platforms that don't do this.

llvm-svn: 192558

llvm-svn: 192557

llvm-svn: 192556

llvm-svn: 192555

llvm-svn: 192554

llvm-svn: 192553

It makes apparently no change it to set this bit or not but the
docs recommand to left it cleared.

llvm-svn: 192552

We were using an anti-pattern of:
 - LoadLibrary
 - GetProcAddress
 - FreeLibrary

This is problematic because of several reasons:
 - We are holding on to pointers into a library we just unloaded.
 - Calling LoadLibrary results in an increase in the reference count of
   the library in question and any libraries that it depends on and
   so-on and so-forth.  This is none too quick.

Instead, use GetModuleHandleEx with GET_MODULE_HANDLE_EX_FLAG_PIN.  This
is done because because we didn't bring the reference for the library
into existence and therefor shouldn't count on it being around later.

llvm-svn: 192550

(This is triggered by current lit tests)

llvm-svn: 192549

* std::string::append(int, int) can be ambiguous.
* std::vector<>::data() is a C++11 feature, use ArrayRef abstraction.

llvm-svn: 192542

Before this patch we relied on the order of phi nodes when we looked for phi
nodes of the same type. This could prevent vectorization of cases where there
was a phi node of a second type in between phi nodes of some type.

This is important for vectorization of an internal graphics kernel. On the test
suite + external on x86_64 (and on a run on armv7s) it showed no impact on
either performance or compile time.

radar://15024459

llvm-svn: 192537

Contributed-by: Peter Zotov <whitequark@whitequark.org>
llvm-svn: 192536

llvm-svn: 192532

llvm-svn: 192527

llvm-svn: 192525

Patch by: Jay Cornwall

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 192523

llvm-svn: 192522

they can be better handled and optimized in the Mips16 constant island code.

llvm-svn: 192520

llvm-svn: 192519

The form must be a reference form in addDIEEntry. Which reference form to
use will be decided by the callee.

No functionality change.

llvm-svn: 192517

This fixes a problem from a previous check-in where a return value was omitted.

Previously the remote/stubs-remote.ll and remote/stubs-sm-pic.ll tests were reporting passes, but they should have been failing.  Those tests attempt to link against an external symbol and remote symbol resolution is not supported.  The old RemoteMemoryManager implementation resulted in local symbols being used for resolution and the child process crashed but the test didn't notice.  With this check-in remote symbol resolution fails, and so the test (correctly) fails.

llvm-svn: 192514

llvm-svn: 192504

llvm-svn: 192501

llvm-svn: 192500

llvm-svn: 192499

llvm-svn: 192492

llvm-svn: 192487

This doesn't change the meaning of the output, but makes look right. PR17539.

llvm-svn: 192483

When if converting something like:
true:
   ... = R0<kill>

false:
   ... = R0<kill>

then the instructions of the true block must not have a <kill> flag
anymore, as the instruction of the false block follow and do still read
the R0 value.
Specifically this patch determines the set of register live-in in the
false block (possibly after simulating the liveness changes of the
duplicated instructions). Each of these live-in registers mustn't be
killed.

llvm-svn: 192482

Contains a set of live register (units) and code to move forward and
backward in the schedule while updating the live set.

llvm-svn: 192481

[DAGCombiner] Load slicing test case: attempt to really fix the buildbots (used sse4.2 instead of avx!).

<rdar://problem/14477220>

llvm-svn: 192480

llvm-svn: 192479

llvm-svn: 192478

Really fix CHECK-LABEL and CHECK-DAG interaction. This actually just restores the initial implementation that was in r186162 but got lost in some subsequent refactoring. More explicit variable names and comments are present now to hopefully prevent repeat regression, as well as another test.

llvm-svn: 192477