llvm-svn: 79747

remove RemoveDuplicateSuccessor, as it is no longer necessary, and because
it breaks assumptions made in
MachineBasicBlock::isOnlyReachableByFallthrough.

Convert test/CodeGen/X86/omit-label.ll to FileCheck and add a testcase
for PR4732.

test/CodeGen/Thumb2/thumb2-ifcvt2.ll sees a diff with this commit due to
it being bugpoint-reduced to the point where it doesn't matter what the
condition for the branch is.

Add some more interesting code to
test/CodeGen/X86/2009-08-06-branchfolder-crash.ll, which is the testcase
that originally motivated the RemoveDuplicateSuccessor code, to help
verify that the original problem isn't being re-broken.

llvm-svn: 79338

preference; no functional change.

llvm-svn: 78391

produced a CFG it wasn't prepared for.

llvm-svn: 78351

This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").

llvm-svn: 75640

Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.

llvm-svn: 75379

sucessor info.

llvm-svn: 71478

suprise to some callers, e.g. register coalescer. For now, add an parameter
that tells AnalyzeBranch whether it's safe to modify the mbb. A better
solution is out there, but I don't have time to deal with it right now.

llvm-svn: 64124

llvm-svn: 63198

llvm-svn: 61950

llvm-svn: 60861

is set but mayLoad is not set. Fix all the problems this turned up.

Change code to not use isSimpleLoad instead of mayLoad unless it
really wants isSimpleLoad.

llvm-svn: 60459

150, based on llvm-test measurements.

llvm-svn: 58225

isReg, etc., from isRegister, etc.

llvm-svn: 57006

llvm-svn: 56469

isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.

llvm-svn: 56189

llvm-svn: 55779

handled correctly, and change a few SmallVector uses to use
size 0 to more clearly reflect their intent.

llvm-svn: 55181

Convert uses of std::vector in TargetInstrInfo to SmallVector.  This change had to be propoagated down into all the targets and up into all clients of this API.

llvm-svn: 54802

to be marked invalid regardless of whether it is
a debug, an exception handling or (hopefully) a
GC label.

llvm-svn: 54172

MachineMemOperands. The pools are owned by MachineFunctions.

This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.

llvm-svn: 53212

predessors of exit blocks from tail merging
consideration.

llvm-svn: 52985

the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.

Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.

This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.

llvm-svn: 52943

llvm-svn: 52495

elements that have been erased.  Based on a patch
by Nicolas Capens.

llvm-svn: 51485

several things that were neither in an anonymous namespace nor static
but not intended to be global.

llvm-svn: 51017

if those blocks consist entirely of common instructions;
merging will not add an extra branch in this case.

llvm-svn: 51006

semantically identical, but little difference in
either results or execution speed; but it's much
easier to read, at least IMO.

llvm-svn: 50999

no functional change.

llvm-svn: 50921

case where there are multiple blocks with a large
number of common tail instructions more efficiently
(compile time optimization).

llvm-svn: 50916

llvm-svn: 50696

Teach branch folding pass about implicit_def instructions. Unfortunately we can't just eliminate them since register scavenger expects every register use to be defined. However, we can delete them when there are no intra-block uses.  Carefully removing some implicit def's which enable more blocks to be optimized away.

llvm-svn: 49461

llvm-svn: 47703

PR1909: Tail merging pass ran wild. It makes no sense to merge blocks in order to save a single instruction since a branch will be inserted for each BB.

llvm-svn: 47301

llvm-svn: 46930

llvm-svn: 46514

Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.

llvm-svn: 45695

that it is cheap and efficient to get.

Move a variety of predicates from TargetInstrInfo into 
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around.  Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.

Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.

llvm-svn: 45674

llvm-svn: 45667

llvm-svn: 45656