quad registers and the Q4PR class holds sets of 4 quad registers.

llvm-svn: 75309

llvm-svn: 75254

llvm-svn: 75250

the cmake build.

llvm-svn: 75246

llvm-svn: 75220

We don't need separate thumb1 instructions tADDSi3 etc. for addc and subc. The "normal" version always modify condition register CPSR so we should just use def : pat to match to the same instructions.

llvm-svn: 75219

llvm-svn: 75218

llvm-svn: 75217

llvm-svn: 75212

llvm-svn: 75206

Use getAsmName() method instead of accessing AsmName field directly.

llvm-svn: 75205

This is part of the fix for pr4521.

llvm-svn: 75201

llvm-svn: 75198

llvm-svn: 75192

Initial support for load / store multiple opt pass Thumb2 support (post-allocation only). It's kind of there, but not quite. I'll return to this later.

llvm-svn: 75190

llvm-svn: 75188

llvm-svn: 75187

Fix ldrd / strd address mode matching code. It allows for +/- 8 bit offset. Also change the printer to make the scale 4 explicit.

Note, we are not yet generating these instructions.

llvm-svn: 75181

llvm-svn: 75173

llvm-svn: 75172

llvm-svn: 75158

llvm-svn: 75153

llvm-svn: 75115

llvm-svn: 75067

- Make bits 25-27 for ldrh, etc. explicitly zero. Previously only the JIT uses the encoding information and it's assuming anything not specified to be zero. Making them explicit so the disassembler is happy.
Patch by Sean Callanan.

llvm-svn: 75065

Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead.

llvm-svn: 75048

Will convert assert(0) that don't have abort() to LLVM_UNREACHABLE in a later
commit.

llvm-svn: 75045

Finish converting lib/Target.

llvm-svn: 75043

llvm-svn: 75037

llvm-svn: 75036

Added ARMBaseRegisterInfo.cpp to lib/Target/ARM/CMakeLists.txt

llvm-svn: 75035

llvm-svn: 75020

llvm-svn: 75019

cerr+abort -> llvm_report_error
assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included)

llvm-svn: 75018

llvm-svn: 75016

Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.

llvm-svn: 75010

these instructions, no autoupgrade or backwards compatibility support is
provided.

llvm-svn: 74991

Add a Thumb2 instruction flag to that indicates whether the instruction can be transformed to 16-bit variant.

llvm-svn: 74988

llvm-svn: 74976

llvm-svn: 74974