llvm-svn: 128650

isn't an exact float. Also "fpext float 1.0 to float" is invalid IR because
it's not performing an extension.

llvm-svn: 128647

Add code to emulate VLD1 (single element to one lane) floating point
register load instruction (ARM) .

llvm-svn: 128646

Turn them into noop KILL instructions instead. This lets the scavenger know when
super-registers are killed and defined.

llvm-svn: 128645

A8.6.23 BLX (immediate)

rdar://problem/9212921

llvm-svn: 128644

llvm-svn: 128643

This way, shrinkToUses() will ignore the instruction that is about to be
deleted, and we avoid leaving invalid live ranges that SplitKit doesn't like.

Fix a misunderstanding in MachineVerifier about <def,undef> operands. The
<undef> flag is valid on def operands where it has the same meaning as <undef>
on a use operand. It only applies to sub-register defines which also read the
full register.

llvm-svn: 128642

llvm-svn: 128641

llvm-svn: 128640

llvm-svn: 128639

Revert changes that caused this scheme to be hidden in certain cases.

llvm-svn: 128638

Add code to emulate VLD1 (multiple single elements) ARM instruction.

llvm-svn: 128637

llvm-svn: 128636

llvm-svn: 128635

llvm-svn: 128634

llvm-svn: 128633

- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
  {STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible.
- Move all instructions which use am2offset without a pattern to use
  addrmode2.
- Add a new encoding bit to describe the index mode used and teach
  printAddrMode2Operand to check by the addressing mode which index
  mode to print.
- Testcases

llvm-svn: 128632

llvm-svn: 128631

llvm-svn: 128630

We don't expect the real "powf()" on some hosts (and powf() would be available on other hosts).
For consistency, std::pow(double,double) may be called instead.
Or, precision issue might attack us, to see unstable regalloc and stack coloring.

llvm-svn: 128629

Thanks Frits!

llvm-svn: 128628

llvm-svn: 128627

llvm-svn: 128626

InstCombine: Shrink "fcmp (fpext x), C" to "fcmp x, C" if C can be losslessly converted to the type of x.

Fixes PR9592.

llvm-svn: 128625

llvm-svn: 128624

llvm-svn: 128623

llvm-svn: 128622

llvm-svn: 128621

llvm-svn: 128620

__block object copy/dispose helpers for C++ objects with those for
different variables with completely different semantics simply because
they happen to both be no more aligned than a pointer.

Found by inspection.

Also, internalize most of the helper generation logic within CGBlocks.cpp,
and refactor it to fit my peculiar aesthetic sense.

llvm-svn: 128618

Add code to emulate VSTR ARM instruction (store a floating point register).

llvm-svn: 128614

Add code to emulate the VLDR Arm instruction (load a floating poitn register).

llvm-svn: 128613

Static analyzer: fix bug in handling of dynamic_cast<>.  The sink node wouldn't always be the final node, thus causing the state to continue propagating.  Instead,
recover some path-sensitivity by conjuring a symbol.

llvm-svn: 128612

Teach static analyzer about the basics of handling new[].  We still don't simulate constructors, but at least the analyzer doesn't think the return value is uninitialized.

llvm-svn: 128611

The rematerialized instruction may require a more constrained register class
than the register being spilled. In the test case, the spilled register has been
inflated to the DPR register class, but we are rematerializing a load of the
ssub_0 sub-register which only exists for DPR_VFP2 registers.

The register class is reinflated after spilling, so the conservative choice is
only temporary.

llvm-svn: 128610

Add "Bits64" utility function.

Add code to emulate VSTM ARM instruction (store multiple floating point registers).

llvm-svn: 128609

change.

llvm-svn: 128608

llvm-svn: 128607

llvm-svn: 128606

llvm-svn: 128605