- Jun 04, 2013
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Venkatraman Govindaraju authored
llvm-svn: 183243
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David Majnemer authored
The ARM backend did not expect LDRBi12 to hold a constant pool operand. Allow for LLVM to deal with the instruction similar to how it deals with LDRi12. This fixes PR16215. llvm-svn: 183238
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Vincent Lejeune authored
llvm-svn: 183229
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Vladimir Medic authored
Test commit for user vmedic, to verify commit access. One line of comment is added to MipsAsmParser.cpp. llvm-svn: 183215
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Aaron Ballman authored
llvm-svn: 183176
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- Jun 03, 2013
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Tom Stellard authored
llvm-svn: 183138
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Tom Stellard authored
llvm-svn: 183137
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Tom Stellard authored
llvm-svn: 183136
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Tom Stellard authored
This is necessary to avoid generating VGPR to SGPR copies in some cases. llvm-svn: 183135
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Tom Stellard authored
llvm-svn: 183134
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Tom Stellard authored
llvm-svn: 183133
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Tom Stellard authored
The CopyToReg nodes will sometimes try to copy a value from a VGPR to an SGPR. This kind of copy is not possible, so we need to detect VGPR->SGPR copies and do something else. The current strategy is to replace these copies with VGPR->VGPR copies and hope that all the users of CopyToReg can accept VGPRs as arguments. llvm-svn: 183132
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Tom Stellard authored
llvm-svn: 183131
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Tom Stellard authored
The lowering of stores is now mostly handled in the tablegen files. No more BUFFER_STORE nodes I generated during legalization. llvm-svn: 183130
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Vincent Lejeune authored
llvm-svn: 183111
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Vincent Lejeune authored
llvm-svn: 183108
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Vincent Lejeune authored
llvm-svn: 183107
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Vincent Lejeune authored
llvm-svn: 183106
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Ahmed Bougacha authored
llvm-svn: 183103
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Venkatraman Govindaraju authored
llvm-svn: 183094
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Venkatraman Govindaraju authored
using two instructions (sethi and store). llvm-svn: 183090
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- Jun 02, 2013
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Venkatraman Govindaraju authored
llvm-svn: 183088
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Venkatraman Govindaraju authored
llvm-svn: 183083
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- Jun 01, 2013
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Venkatraman Govindaraju authored
llvm-svn: 183079
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Tim Northover authored
Very sorry, it was committed from the wrong branch by mistake. llvm-svn: 183070
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Tim Northover authored
llvm-svn: 183069
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Tim Northover authored
The MOV64ri64i32 instruction required hacky MCInst lowering because it was allocated as setting a GR64, but the eventual instruction ("movl") only set a GR32. This converts it into a so-called "MOV32ri64" which still accepts a (appropriate) 64-bit immediate but defines a GR32. This is then converted to the full GR64 by a SUBREG_TO_REG operation, thus keeping everyone happy. This fixes a typo in the opcode field of the original patch, which should make the legact JIT work again (& adds test for that problem). llvm-svn: 183068
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Venkatraman Govindaraju authored
llvm-svn: 183067
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Ahmed Bougacha authored
This also makes TableGen able to compute sizes/offsets of synthesized indices representing tuples. llvm-svn: 183061
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Eric Christopher authored
seems to have caused PR16192 and other JIT related failures. llvm-svn: 183059
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- May 31, 2013
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Benjamin Kramer authored
Fixes a leak found by valgrind. llvm-svn: 183031
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Ahmed Bougacha authored
NOTE: If this broke your out-of-tree backend, in *RegisterInfo.td, change the instances of SubRegIndex that have a comps template arg to use the ComposedSubRegIndex class instead. In TableGen land, this adds Size and Offset attributes to SubRegIndex, and the ComposedSubRegIndex class, for which the Size and Offset are computed by TableGen. This also adds an accessor in MCRegisterInfo, and Size/Offsets for the X86 and ARM subreg indices. llvm-svn: 183020
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Tim Northover authored
Patch by Amaury de la Vieuville. llvm-svn: 183012
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Tim Northover authored
These instructions are deprecated oddities, but we still need to be able to disassemble (and reassemble) them if and when they're encountered. Patch by Amaury de la Vieuville. llvm-svn: 183011
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Tim Northover authored
The disassembly of VEXT instructions was too lax in the bits checked. This fixes the case where the instruction affects Q-registers but a misaligned lane was specified (should be UNDEFINED). Patch by Amaury de la Vieuville llvm-svn: 183003
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Richard Sandiford authored
Unlike most -- hopefully "all other", but I'm still checking -- memory instructions we support, LOAD REVERSED and STORE REVERSED may access the memory location several times. This means that they are not suitable for volatile loads and stores. This patch is a prerequisite for better atomic load and store support. The same principle applies there: almost all memory instructions we support are inherently atomic ("block concurrent"), but LOAD REVERSED and STORE REVERSED are exceptions. Other instructions continue to allow volatile operands. I will add positive "allows volatile" tests at the same time as the "allows atomic load or store" tests. llvm-svn: 183002
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Justin Holewinski authored
Now that 3.3 is branched, we are re-enabling virtual registers to help iron out bugs before the next release. Some of the post-RA passes do not play well with virtual registers, so we disable them for now. The needed functionality of the PrologEpilogInserter pass is copied to a new backend-specific NVPTXPrologEpilog pass. The test for this commit is not breaking the existing tests. llvm-svn: 182998
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Tim Northover authored
The MOV64ri64i32 instruction required hacky MCInst lowering because it was allocated as setting a GR64, but the eventual instruction ("movl") only set a GR32. This converts it into a so-called "MOV32ri64" which still accepts a (appropriate) 64-bit immediate but defines a GR32. This is then converted to the full GR64 by a SUBREG_TO_REG operation, thus keeping everyone happy. llvm-svn: 182991
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Akira Hatanaka authored
Patch by Jyun-Yan You. llvm-svn: 182984
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- May 30, 2013
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Rafael Espindola authored
r182877 broke MCJIT tests on ARM and r182937 was working around another failure by r182877. This should make the ARM bots green. llvm-svn: 182960
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