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  1. Jun 04, 2013
  2. Jun 03, 2013
  3. Jun 02, 2013
  4. Jun 01, 2013
  5. May 31, 2013
    • Benjamin Kramer's avatar
      NVPTX: Don't even create a regalloc if we're not going to use it. · fae7ff12
      Benjamin Kramer authored
      Fixes a leak found by valgrind.
      
      llvm-svn: 183031
      fae7ff12
    • Ahmed Bougacha's avatar
      Add a way to define the bit range covered by a SubRegIndex. · f1ed334d
      Ahmed Bougacha authored
      NOTE: If this broke your out-of-tree backend, in *RegisterInfo.td, change
      the instances of SubRegIndex that have a comps template arg to use the
      ComposedSubRegIndex class instead.
      
      In TableGen land, this adds Size and Offset attributes to SubRegIndex,
      and the ComposedSubRegIndex class, for which the Size and Offset are
      computed by TableGen. This also adds an accessor in MCRegisterInfo, and
      Size/Offsets for the X86 and ARM subreg indices.
      
      llvm-svn: 183020
      f1ed334d
    • Tim Northover's avatar
      ARM: permit upper-case BE/LE on setend instruction · 4d141440
      Tim Northover authored
      Patch by Amaury de la Vieuville.
      
      llvm-svn: 183012
      4d141440
    • Tim Northover's avatar
      ARM: add fstmx and fldmx instructions for assembly · 4173e29a
      Tim Northover authored
      These instructions are deprecated oddities, but we still need to be able to
      disassemble (and reassemble) them if and when they're encountered.
      
      Patch by Amaury de la Vieuville.
      
      llvm-svn: 183011
      4173e29a
    • Tim Northover's avatar
      ARM: fix VEXT encoding corner case · 1bb672da
      Tim Northover authored
      The disassembly of VEXT instructions was too lax in the bits checked. This
      fixes the case where the instruction affects Q-registers but a misaligned lane
      was specified (should be UNDEFINED).
      
      Patch by Amaury de la Vieuville
      
      llvm-svn: 183003
      1bb672da
    • Richard Sandiford's avatar
      [SystemZ] Don't use LOAD and STORE REVERSED for volatile accesses · 30efd87f
      Richard Sandiford authored
      Unlike most -- hopefully "all other", but I'm still checking -- memory
      instructions we support, LOAD REVERSED and STORE REVERSED may access
      the memory location several times.  This means that they are not suitable
      for volatile loads and stores.
      
      This patch is a prerequisite for better atomic load and store support.
      The same principle applies there: almost all memory instructions we
      support are inherently atomic ("block concurrent"), but LOAD REVERSED
      and STORE REVERSED are exceptions.
      
      Other instructions continue to allow volatile operands.  I will add
      positive "allows volatile" tests at the same time as the "allows atomic
      load or store" tests.
      
      llvm-svn: 183002
      30efd87f
    • Justin Holewinski's avatar
      [NVPTX] Re-enable support for virtual registers in the final output · dbb3b2f4
      Justin Holewinski authored
      Now that 3.3 is branched, we are re-enabling virtual registers to help
      iron out bugs before the next release. Some of the post-RA passes do
      not play well with virtual registers, so we disable them for now. The
      needed functionality of the PrologEpilogInserter pass is copied to a
      new backend-specific NVPTXPrologEpilog pass.
      
      The test for this commit is not breaking the existing tests.
      
      llvm-svn: 182998
      dbb3b2f4
    • Tim Northover's avatar
      X86: change MOV64ri64i32 into MOV32ri64 · d4736d67
      Tim Northover authored
      The MOV64ri64i32 instruction required hacky MCInst lowering because it was
      allocated as setting a GR64, but the eventual instruction ("movl") only set a
      GR32. This converts it into a so-called "MOV32ri64" which still accepts a
      (appropriate) 64-bit immediate but defines a GR32. This is then converted to
      the full GR64 by a SUBREG_TO_REG operation, thus keeping everyone happy.
      
      llvm-svn: 182991
      d4736d67
    • Akira Hatanaka's avatar
      [mips] Big-endian code generation for atomic instructions. · 2bf97336
      Akira Hatanaka authored
      Patch by Jyun-Yan You.
      
      llvm-svn: 182984
      2bf97336
  6. May 30, 2013
    • Rafael Espindola's avatar
      Revert r182937 and r182877. · 99bd2ae4
      Rafael Espindola authored
      r182877 broke MCJIT tests on ARM and r182937 was working around another failure
      by r182877.
      
      This should make the ARM bots green.
      
      llvm-svn: 182960
      99bd2ae4
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