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  1. May 14, 2007
  2. May 03, 2007
  3. May 02, 2007
  4. May 01, 2007
  5. Apr 26, 2007
  6. Apr 25, 2007
    • Evan Cheng's avatar
      Fix for PR1306. · 7818c03c
      Evan Cheng authored
      - A register def / use now implicitly affects sub-register liveness but does
      not affect liveness information of super-registers.
      - Def of a larger register (if followed by a use later) is treated as
      read/mod/write of a smaller register.
      
      llvm-svn: 36434
      7818c03c
  7. Apr 18, 2007
  8. Apr 17, 2007
    • Evan Cheng's avatar
      Copy coalescing change to prevent a physical register from being pin to a · b881bdab
      Evan Cheng authored
      long live interval that has low usage density.
      1. Change order of coalescing to join physical registers with virtual
         registers first before virtual register intervals become too long.
      2. Check size and usage density to determine if it's worthwhile to join.
      3. If joining is aborted, assign virtual register live interval allocation
         preference field to the physical register.
      4. Register allocator should try to allocate to the preferred register
         first (if available) to create identify moves that can be eliminated.
      
      llvm-svn: 36218
      b881bdab
  9. Apr 04, 2007
  10. Apr 02, 2007
  11. Mar 30, 2007
  12. Mar 28, 2007
  13. Mar 27, 2007
  14. Mar 22, 2007
  15. Mar 20, 2007
  16. Mar 19, 2007
  17. Mar 18, 2007
  18. Mar 17, 2007
    • Evan Cheng's avatar
      Joining a live interval of a physical register with a virtual one can turn out · 7b2a0016
      Evan Cheng authored
      to be really bad. Once they are joined they are not broken apart. Also, physical
      intervals cannot be spilled!
      
      Added a heuristic as a workaround for this. Be careful coalescing with a
      physical register if the virtual register uses are "far". Check if there are
      uses in the same loop as the source (copy instruction). Check if it is in the
      loop preheader, etc.
      
      llvm-svn: 35134
      7b2a0016
  19. Mar 15, 2007
  20. Mar 03, 2007
    • Evan Cheng's avatar
      Watch out for cases like this: · 3fd72859
      Evan Cheng authored
      entry (0x8b056f0, LLVM BB @0x8b01b30, ID#0):
      Live Ins: %r0 %r1 %r2 %r3
              %reg1032 = tMOVrr %r3<kill>
              %reg1033 = tMOVri8 1
              %reg1034 = tMOVri8 0
              tCMPi8 %reg1029<kill>, 0
              tBcc mbb<entry,0x8b06a10>, 0
          Successors according to CFG: 0x8b06980 0x8b06a10
      
      entry (0x8b06980, LLVM BB @0x8b01b30, ID#12):
          Predecessors according to CFG: 0x8b056f0
              %reg1036 = tMOVrr %reg1034<kill>
          Successors according to CFG: 0x8b06a10
      
      entry (0x8b06a10, LLVM BB @0x8b01b30, ID#13):
          Predecessors according to CFG: 0x8b056f0 0x8b06980
              %reg1024<dead> = tMOVrr %reg1030<kill>
              ...
      
      reg1030 and r1 have already been joined. When reg1024 and reg1030 are joined,
      r1 live range from function entry to the tMOVrr instruction are dead. Eliminate
      r1 from the livein set of the entry BB, not the BB where the copy is.
      
      llvm-svn: 34866
      3fd72859
  21. Mar 02, 2007
  22. Mar 01, 2007
  23. Feb 26, 2007
  24. Feb 25, 2007
  25. Feb 23, 2007
  26. Feb 21, 2007
  27. Feb 19, 2007
  28. Feb 17, 2007
  29. Feb 15, 2007
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