that many of these things, so the memory savings isn't significant,
and there are now situations where there can be alignments greater
than 128.

llvm-svn: 110836

avoids trouble if the return type of TD->getPointerSize() is
changed to something which doesn't promote to a signed type,
and is simpler anyway.

Also, use getCopyFromReg instead of getRegister to read a
physical register's value.

llvm-svn: 110835

llvm-svn: 110826

llvm-svn: 110810

float t1(int argc) {
  return (argc == 1123) ? 1.234f : 2.38213f;
}

We would generate truly awful code on ARM (those with a weak stomach should look
away):

_t1:
  movw   r1, #1123
  movs   r2, #1
  movs   r3, #0
  cmp    r0, r1
  mov.w  r0, #0
  it     eq
  moveq  r0, r2
  movs   r1, #4
  cmp    r0, #0
  it     ne
  movne  r3, r1
  adr    r0, #LCPI1_0
  ldr    r0, [r0, r3]
  bx     lr

The problem was that legalization was creating a cascade of SELECT_CC nodes, for
for the comparison of "argc == 1123" which was fed into a SELECT node for the ?:
statement which was itself converted to a SELECT_CC node. This is because the
ARM back-end doesn't have custom lowering for SELECT nodes, so it used the
default "Expand".

I added a fairly simple "LowerSELECT" to the ARM back-end. It takes care of this
testcase, but can obviously be expanded to include more cases.

Now we generate this, which looks optimal to me:

_t1:
  movw   r1, #1123
  movs   r2, #0
  cmp    r0, r1
  adr    r0, #LCPI0_0
  it     eq
  moveq  r2, #4
  ldr    r0, [r0, r2]
  bx     lr
  .align  2
LCPI0_0:
  .long   1075344593  @ float 2.382130e+00
  .long   1067316150  @ float 1.234000e+00

llvm-svn: 110799

Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors.

llvm-svn: 110798

llvm-svn: 110797

llvm-svn: 110796

llvm-svn: 110795

MC/ARM: Add basic support for handling predication by parsing it out of the mnemonic into a separate operand form.

llvm-svn: 110794

llvm-svn: 110793

llvm-svn: 110792

llvm-mc: Add -show-inst-operands, for dumping the parsed instruction representation before matching.

llvm-svn: 110791

llvm-svn: 110790

llvm-svn: 110788

llvm-svn: 110787

instructions: dmb, dsb, isb, msr, and mrs.

llvm-svn: 110786

  memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
  instructions).
- Added tests for memory barrier codegen.

llvm-svn: 110785

llvm-svn: 110783

llvm-svn: 110782

for some reason they have a very odd MCInst form where the operands overlap, but
I haven't dug in to find out why yet.

llvm-svn: 110781

llvm-svn: 110780

llvm-svn: 110778

llvm-svn: 110762

llvm-svn: 110761

make any assumptions about when the two conditions will agree on when
to permit the loop to exit. This fixes PR7845.

llvm-svn: 110758

(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!!  Two of them were already out of sync.  I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.)  Add support for encoding these instructions.

llvm-svn: 110754

llvm-svn: 110750

llvm-svn: 110745

Apply the same approach of SSE4.1 ptest intrinsics but
create a new x86 node "testp" since AVX introduces
vtest{ps}{pd} instructions which set ZF and CF depending
on sign bit AND and ANDN of packed floating-point sources.

This is slightly different from what the "ptest" does.
Tests comming with the other 256 intrinsics tests.

llvm-svn: 110744

create constraints from comparisons other than eq/neq.

llvm-svn: 110742

patterns generated by clang for transpose of a matrix in generic vectors.  This is made
of two parts:

1) Propagating vector extracts of hi/lo half into their users
2) Recognizing an insertion of even elements followed by the odd elements as an unpack.

Testcase to come, but this shrinks the # of shuffle instructions generated on x86 from ~40 to the minimal 8.

llvm-svn: 110734

a register before checking if it was defined.

llvm-svn: 110733

operands. We don't currently have a hook to provide "the largest super class of
A where all registers' getSubReg(subidx) is valid and in B".

llvm-svn: 110730

llvm-svn: 110726

The live interval may be used for a spill slot as well, and that spill slot
could be shared by split registers. We cannot shrink it, even if we know the
current register won't need the spill slot in that range.

llvm-svn: 110721

llvm-svn: 110720

ARM testers.

llvm-svn: 110718

llvm-svn: 110717

llvm-svn: 110714