llvm-svn: 35430

llvm-svn: 35429

llvm-svn: 35406

llvm-svn: 35394

system assembler not groking legal instructions like "leal (,%esi,8), %ecx".

llvm-svn: 35393

llvm-svn: 35392

the MMX instructions that are needed...

llvm-svn: 35389

comparison operators.

llvm-svn: 35385

char" and it is up to the compilers implementation or the platform which is
followed."
http://www.arm.linux.org.uk/docs/faqs/signedchar.php

llvm-svn: 35382

llvm-svn: 35381

llvm-svn: 35366

llvm-svn: 35353

llvm-svn: 35352

#include <mmintrin.h>

extern __m64 C;

void baz(__v2si *A, __v2si *B)
{
  *A = C;
  _mm_empty();
}

We get this:

_baz:
        call "L1$pb"
"L1$pb":
        popl %eax
        movl L_C$non_lazy_ptr-"L1$pb"(%eax), %eax
        movq (%eax), %mm0
        movl 4(%esp), %eax
        movq %mm0, (%eax)
        emms
        ret

GCC gives us this:

_baz:
        pushl   %ebx
        call    L3
"L00000000001$pb":
L3:
        popl    %ebx
        subl    $8, %esp
        movl    L_C$non_lazy_ptr-"L00000000001$pb"(%ebx), %eax
        movl    (%eax), %edx
        movl    4(%eax), %ecx
        movl    16(%esp), %eax
        movl    %edx, (%eax)
        movl    %ecx, 4(%eax)
        emms
        addl    $8, %esp
        popl    %ebx
        ret

llvm-svn: 35351

llvm-svn: 35337

llvm-svn: 35334

llvm-svn: 35330

llvm-svn: 35329

not just the first letter.  No functionality change.

llvm-svn: 35322

Allow the b/h/w/k constraints to be applied to values that have multiple alternatives, and end up not being registers.

llvm-svn: 35320

llvm-svn: 35319

llvm-svn: 35318

llvm-svn: 35296

llvm-svn: 35292

Add final support to get the QT example to compile.

llvm-svn: 35290

intrinsic.

llvm-svn: 35269

llvm-svn: 35266

llvm-svn: 35245

llvm-svn: 35244

llvm-svn: 35242

llvm-svn: 35241

is the frame pointer.

llvm-svn: 35233

llvm-svn: 35230

llvm-svn: 35229

instructions (that would have to be split later)

llvm-svn: 35227

    mov lr, pc
    bx lr
So, the function was not called.

llvm-svn: 35218

Make two piece constant generation as a single instruction. It's re-materialized as a load from constantpool.

llvm-svn: 35207

llvm-svn: 35206

llvm-svn: 35205

1) codegen a shift of a register as a shift, not an LEA.
2) teach the RA to convert a shift to an LEA instruction if it wants something
   in three-address form.

This gives us asm diffs like:

-       leal (,%eax,4), %eax
+       shll $2, %eax

which is faster on some processors and smaller on all of them.

and, more interestingly:

-       movl 24(%esi), %eax
-       leal (,%eax,4), %edi
+       movl 24(%esi), %edi
+       shll $2, %edi

Without #2, #1 was a significant pessimization in some cases.

This implements CodeGen/X86/shift-codegen.ll

llvm-svn: 35204