llvm-svn: 93614

llvm-svn: 93612

llvm-svn: 93610

llvm-svn: 93609

llvm-svn: 93608

on the build bots.

llvm-svn: 93606

llvm-svn: 93605

Note that the code wasn't calling DecorateCygMingName
when emitting the ".ascii -export" stuff at the end of
file for DLLExported functions.  I don't know if it should
or not, but I'm preserving behavior.

llvm-svn: 93603

not during the later post-alloc tail duplication.

llvm-svn: 93600

llvm-svn: 93598

the -pre-regalloc-taildup command-line option, and add a new
-disable-early-taildup option.

llvm-svn: 93597

llvm-svn: 93595

and CurrentFnName.

llvm-svn: 93594

llvm-svn: 93590

replace it.  Upgrade Alpha, Blackfin, and part of CellSPU to not
use mangler anymore.  CellSPU needs more invasive surgery.

llvm-svn: 93589

llvm-svn: 93587

llvm-svn: 93582

BumpPtrAllocator: Have the DefaultSlabAllocator created at runtime, not initialization time.  This removes one of the 'init_constructors' reported in <rdar://problem/7545356>.

llvm-svn: 93581

llvm-svn: 93580

llvm-svn: 93578

llvm-svn: 93577

Fix PR6019.  A load has more than one use if it feeds a bitconvert that
has more than one use.

llvm-svn: 93576

helper method, use it to simplify some code.

llvm-svn: 93575

llvm-svn: 93571

llvm-svn: 93570

target-dependent memory address representation in it.
Restore X86 printing of DEBUG_VALUE; lowering is
done in X86RegisterInfo using the normal algorithm.

llvm-svn: 93565

handle physical registers R0-R7 when described as having a non-tGPR register
class.

llvm-svn: 93564

llvm-svn: 93563

llvm-svn: 93562

llvm-svn: 93560

users.

llvm-svn: 93558

llvm-svn: 93556

llvm-svn: 93554

llvm-svn: 93553

llvm-svn: 93552

Add micro-optimization which allows us to fold imm into cmp. This allows us to save 1 word (sometimes) and reduce register pressure.

llvm-svn: 93551

llvm-svn: 93550

This fixes the regression for -pre-regalloc-taildup in
MultiSource/Applications/lambda-0.1.3.

llvm-svn: 93541

llvm-svn: 93540

llvm-svn: 93539