v2i64 needs to be a legal VSX type because it is the SetCC result type from
v2f64 comparisons. We need to expand all non-arithmetic v2i64 operations.

This fixes the lowering for v2f64 VSELECT.

llvm-svn: 204828

llvm-svn: 204827

This enables TableGen to generate an additional two operand matcher
for our ArithLogicR class of instructions (constituted by 3 register operands).
E.g.: and $1, $2 <=> and $1, $1, $2

llvm-svn: 204826

Fixes PR19253.

llvm-svn: 204825

llvm-svn: 204824

The interceptors had code that after macro expansion ended up looking like

extern "C" void memalign()
    __attribute__((weak, alias("__interceptor_memalign")));
extern "C" void __interceptor_memalign() {}
extern "C" void __interceptor___libc_memalign()
    __attribute__((alias("memalign")));

That is,
* __interceptor_memalign is a function
* memalign is a weak alias to __interceptor_memalign
* __interceptor___libc_memalign is an alias to memalign

Both gcc and clang produce assembly that look like

__interceptor_memalign:
...
        .weak   memalign
memalign = __interceptor_memalign
        .globl  __interceptor___libc_memalign
__interceptor___libc_memalign = memalign

What it means in the end is that we have 3 symbols pointing to the
same position in the file, one of which is weak:

     8: 0000000000000000     1 FUNC    GLOBAL DEFAULT    1
__interceptor_memalign
     9: 0000000000000000     1 FUNC    WEAK   DEFAULT    1 memalign
    10: 0000000000000000     1 FUNC    GLOBAL DEFAULT    1
__interceptor___libc_memalign

In particular, note that __interceptor___libc_memalign will always
point to __interceptor_memalign, even if we do link in a strong symbol
for memalign. In fact, the above code produces exactly the same binary
as

extern "C" void memalign()
    __attribute__((weak, alias("__interceptor_memalign")));
extern "C" void __interceptor_memalign() {}
extern "C" void __interceptor___libc_memalign()
    __attribute__((alias("__interceptor_memalign")));

If nothing else, this patch makes it more obvious what is going on.

llvm-svn: 204823

The '.dword' directive accepts a list of expressions and emits
them in 8-byte chunks in successive locations.

llvm-svn: 204822

The main difference between __va_start and __builtin_va_start is that
the address of the va_list has already been taken, and the va_list is
always a char*.

__va_end and __va_arg are not needed.

llvm-svn: 204821

Adding the mapping between __builtin___clear_cache into @llvm.clear_cache

llvm-svn: 204820

up as jump table or other forms of branches on the machine level.

llvm-svn: 204819

parseDirectiveWord is a generic function that parses an expression which
means there's no need for it to have such an specific name. Renaming it to
parseDataDirective so that it can also be used to handle .dword directives[1].

[1]To be added in a follow up commit.

No functional changes.

llvm-svn: 204818

The '.set mips64' directive enables the feature Mips:FeatureMips64
from assembly. Note that it doesn't modify the ELF header as opposed
to the use of -mips64 from the command-line. The reason for this
is that we want to be as compatible as possible with existing assemblers
like GAS.

llvm-svn: 204817

llvm-svn: 204816

The '.set mips64r2' directive enables the feature Mips:FeatureMips64r2
from assembly. Note that it doesn't modify the ELF header as opposed
to the use of -mips64r2 from the command-line. The reason for this
is that we want to be as compatible as possible with existing assemblers
like GAS.

llvm-svn: 204815

llvm-svn: 204814

We've already got versions without the barriers, so this just adds IR-level
support for generating the new v8 ones.

rdar://problem/16227836

llvm-svn: 204813

llvm-svn: 204812

    
Given that we support multiple directives that enable a particular feature
(e.g. '.set mips16'), it's best to hoist that code into a new function
so that we don't repeat the same pattern w.r.t parsing and handling error cases.

No functional changes.

llvm-svn: 204811

llvm-svn: 204810

ReportRace takes the two mutexes in the opposite order

llvm-svn: 204809

newer gcc inserts memset here

llvm-svn: 204808

Patch by Gabor Ballabas.

llvm-svn: 204807

After some discussion on IRC, emitting a call to the library function seems
like a better default, since it will move from a compiler internal error to
a linker error, that the user can work around until LLVM is fixed.

I'm also adding a note on the responsibility of the user to confirm that
the cache was cleared on platforms where nothing is done.

llvm-svn: 204806

[mips] The decision to use MO_GOT_PAGE and MO_GOT_OFST depends on the ABI being N32 or N64 not the arch being MIPS64

Summary: No functional change (in supported use cases)

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3177

llvm-svn: 204805

llvm-svn: 204804

The directive '.option pic2' enables PIC from assembly source.
At the moment none of the macros/directives check the PIC bit
but that's going to be fixed relatively soon. For example, the
expansion of macros like 'la' depend on the relocation model.

llvm-svn: 204803

Implementing the LLVM part of the call to __builtin___clear_cache
which translates into an intrinsic @llvm.clear_cache and is lowered
by each target, either to a call to __clear_cache or nothing at all
incase the caches are unified.

Updating LangRef and adding some tests for the implemented architectures.
Other archs will have to implement the method in case this builtin
has to be compiled for it, since the default behaviour is to bail
unimplemented.

A Clang patch is required for the builtin to be lowered into the
llvm intrinsic. This will be done next.

llvm-svn: 204802

With VSX there is a real vector select instruction, and so we should use it.
Note that VSELECT will still scalarize for v2f64 because the corresponding
SetCC result type (v2i64) is not currently a legal type.

llvm-svn: 204801

llvm-svn: 204800

llvm-svn: 204799

NetBSD/aarch64 to simplify code sharing with NetBSD/arm.

llvm-svn: 204798

These are aliases of t4-t7 and are provided for compatibility with both the
original ABI documentation (using t4-t7) and GNU As (using t0-t3)

llvm-svn: 204797

Summary: Added test cases for O32 and N32 on MIPS64.

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3175

llvm-svn: 204796

llvm-svn: 204795

llvm-svn: 204794

llvm-svn: 204793

[mips] Move the CHECK lines in mips*-register-names.s to make it more obvious which CHECK matches with which insn

This reveals a small mistake in mips-register-names.s ($sp is tested twice and
$s8 is not tested) which will be fixed in a follow-up commit.

llvm-svn: 204792

llvm-svn: 204791

Fix PR19239 - Add support for generating debug info for functions without lexical scopes and/or debug info at all

llvm-svn: 204790

llvm-svn: 204788