lower them to the correct x86-64 instructions since we 
don't have a clean way to handle this in td files yet.
rdar://7947184

llvm-svn: 103668

Fix some potential issues in the pseudo instruction expansion phase: copy implicit operands and memoperands. Also, expand instructions even if their defs are "dead" since they may have implicit kill operands.

llvm-svn: 103667

llvm-svn: 103665

llvm-svn: 103664

llvm-svn: 103663

MC: Switch MCFillFragment to storing total fill size instead of a count. This allows using ValueSize==0 to represent a virtual fill.

llvm-svn: 103662

MCAlignFragments for this.

llvm-svn: 103661

part first.  rdar://7947184

llvm-svn: 103660

on RAUW of functions, this is a correctness issue instead of a mere memory
usage problem.


No testcase until the new MergeFunctions can land.

llvm-svn: 103653

llvm-svn: 103651

llvm-svn: 103649

llvm-svn: 103648

llvm-svn: 103642

The X86 floating point stack pass and others depend on good kill flags.

llvm-svn: 103635

llvm-svn: 103627

llvm-svn: 103616

Made a stylistic changed to the code/comments related to the unsupported COMDAT selection  type IMAGE_COMDAT_SELECT_LARGEST based on from Anton Korobeynikov.

llvm-svn: 103590

llvm-svn: 103586

llvm-svn: 103576

Now, the .linkonce directive is emitted as part of MCSectionCOFF::PrintSwitchToSection instead of AsmPrinter::EmitLinkage since it is an attribute of the section the symbol was placed into not the symbol itself.

llvm-svn: 103568

v1024 = REG_SEQUENCE ...
v1025 = EXTRACT_SUBREG v1024, 5
v1026 = EXTRACR_SUBREG v1024, 6
      = VSTxx <addr>, v1025, v1026

The REG_SEQUENCE ensures the sources that feed into the VST instruction
are getting the right register allocation so they form a large super-
register. The extract_subreg will be coalesced away all would just work:
v1024 = REG_SEQUENCE ...
      = VSTxx <addr>, v1024:5, v1024:6

The problem is if the coalescer isn't run, the extract_subreg instructions
would stick around and there is no assurance v1025 and v1026 will get the
right registers.

As a short term workaround, teach the NEON pre-allocation pass to transfer
the sub-register indices over. An alternative would be do it 2addr pass
when reg_sequence's are eliminated. But that *seems* wrong and require
updating liveness information.

Another alternative is to do this in the scheduler when the instructions are
created. But that would mean somehow the scheduler this has to be done for
correctness reason. That's yucky as well. So for now, we are leaving this
in the target specific pass.

llvm-svn: 103540

llvm-svn: 103539

llvm-svn: 103538

llvm-svn: 103535

be diced into atoms, and adjust getAtom() to take this into account.
 - This fixes relocations to symbols in fixed size literal sections, for
   example.

llvm-svn: 103532

llvm-svn: 103530

llvm-svn: 103529

llvm-svn: 103528

offset instead of the fixup address as intended.

llvm-svn: 103527

llvm-svn: 103526

llvm-svn: 103525

llvm-svn: 103522

This allows us to add accurate kill markers, something the scavenger likes.
Add some more tests from ARM that needed this.

llvm-svn: 103521

create separate virtual registers for CopyFromReg values, so uses of
them don't necessarily kill the value.

llvm-svn: 103519

llvm-svn: 103513

llvm-svn: 103508

llvm-svn: 103507

closure after allocating all blocks.

Add a few more test cases for -regalloc=fast.

llvm-svn: 103500

It works in simple cases, but it isn't a general solution.

llvm-svn: 103499

to LLVM_LIBRARY_VISIBILITY and introduce LLVM_GLOBAL_VISIBILITY, which is
the opposite, for future use by dragonegg.

llvm-svn: 103495