Add explicit VEX_L tags to all 256-bit instructions. This will allow us to remove code from the code emitters that examined operands to set the L-bit.

llvm-svn: 164202

llvm-svn: 164169

llvm-svn: 164155

llvm-svn: 164150

Patch by Adhemerval Zanella.

llvm-svn: 164141

llvm-svn: 164139

Patch by Adhemerval Zanella.

llvm-svn: 164138

store this and use it to not emit long nops when the CPU is geode which
doesnt support them.

Fixes PR11212.

llvm-svn: 164132

More domain conversion; convert VFP VMOVS to NEON instructions in more cases - when we may clobber the other S-lane by converting an S to a D instruction, make an effort to work out if the S lane is clobberable or not.

llvm-svn: 164114

llvm-svn: 164092

aligned address. Based on patch by David Peixotto.

Also use vld1.64 / vst1.64 with 128-bit alignment to take advantage of alignment
hints. rdar://12090772, rdar://12238782

llvm-svn: 164089

I have to work out the Target/CodeGen header dependencies
before putting this back.

llvm-svn: 164072

llvm-svn: 164061

While we are setting the earlier def to true, also make it live.

llvm-svn: 164056

we will do that when we implement the full save/restore.

Patch by Reed Kotler.

llvm-svn: 164051

LLVM_ATTRIBUTE_USED forces emission of a function. To silence unused function warnings use LLVM_ATTRIBUTE_UNUSED.

llvm-svn: 164036

llvm-svn: 164030

llvm-svn: 164001

It had patterns for zext-loading and extending. This commit adds patterns for loading a wide type, performing a bitcast,
and extending. This is an odd pattern, but it is commonly used when writing code with intrinsics.

rdar://11897677

llvm-svn: 163995

llvm-svn: 163974

llvm-svn: 163973

This was only an issue if sse is disabled.

llvm-svn: 163967

use load/store fragments defined in TargetSelectionDAG.td in place of them.
Unaligned loads/stores are either expanded or lowered to target-specific nodes,
so instruction selection should see only aligned load/store nodes.

No changes in functionality.

llvm-svn: 163960

Patch by Reed Kotler.

llvm-svn: 163956

llvm-svn: 163922

This models the A9 processor at the level of instruction operands, as
opposed to the itinerary, which models each operation at the level of
pipeline stages.

The two primary motivations are:

1) Allow MachineScheduler to model A9 as an out-of-order processor. It
can now distinguish between hazards that force interlocking vs.
buffered resources.

2) Reduce long-term maintenance by allowing the itinerary and target
hooks to eventually be removed. Note that almost all of the complexity
in the new model exists to model instruction variants, which the
itinerary cannot handle. Instead the scheduler previously relied on
processor-specific target hooks which are incomplete and buggy.

llvm-svn: 163921

This patch introduces a possibility for Hexagon MI scheduler
to perform some target specific post- processing on the scheduling
DAG prior to scheduling.

llvm-svn: 163903

* wrap code blocks in \code ... \endcode;
* refer to parameter names in paragraphs correctly (\arg is not what most
  people want -- it starts a new paragraph);
* use \param instead of \arg to document parameters in order to be consistent
  with the rest of the codebase.

llvm-svn: 163902

clang warned about this being unused in Release builds.

llvm-svn: 163899

1. Add MoveR3216
2. Correct spelling for Move32R16

Patch by Reed Kotler.

llvm-svn: 163869

llvm-svn: 163835

- Enhance the fix to PR12312 to support wider integer, such as 256-bit
  integer. If more than 1 fully evaluated vectors are found, POR them
  first followed by the final PTEST.

llvm-svn: 163832

Add a PatFrag to match X86tcret using 6 fixed registers or less. This
avoids folding loads into TCRETURNmi64 using 7 or more volatile
registers.

<rdar://problem/12282281>

llvm-svn: 163819

immediate operands to be copied.

Patch by Reed Kotler.

llvm-svn: 163811

The patch caused "Wrong topological sorting" assertions.

llvm-svn: 163810

llvm-svn: 163803

Add a new compression type to ModRM table that detects when the memory modRM byte represent 8 instructions and the reg modRM byte represents up to 64 instructions. Reduces modRM table from 43k entreis to 25k entries. Based on a patch from Manman Ren.

llvm-svn: 163774

We don't have enough GR64_TC registers when calling a varargs function
with 6 arguments. Since %al holds the number of vector registers used,
only %r11 is available as a scratch register.

This means that addressing modes using both base and index registers
can't be folded into TCRETURNmi64.

<rdar://problem/12282281>

llvm-svn: 163761

1. Remove RA from list of allocatable registers
2. Enable d,y,r constraint inline assembly instructions

Patch by Reed Kotler.

llvm-svn: 163753

    
- BlockAddress has no support of BA + offset form and there is no way to
  propagate that offset into machine operand;
- Add BA + offset support and a new interface 'getTargetBlockAddress' to
  simplify target block address forming;
- All targets are modified to use new interface and X86 backend is enhanced to
  support BA + offset addressing.

llvm-svn: 163743