into i16/i32 load/stores.

llvm-svn: 29089

llvm-svn: 29011

dropped.  This shrinks libllvmgcc.dylib another 67K

llvm-svn: 28975

llvm-svn: 28971

llvm-svn: 28944

llvm-svn: 28941

llvm-svn: 28936

llvm-svn: 28935

and the data

llvm-svn: 28934

the offset two bits to the left.

llvm-svn: 28933

llvm-svn: 28932

llvm-svn: 28931

llvm-svn: 28930

llvm-svn: 28929

llvm-svn: 28927

llvm-svn: 28926

ppc64 mode!

llvm-svn: 28923

llvm-svn: 28922

doesn't work right).

llvm-svn: 28921

llvm-svn: 28920

llvm-svn: 28919

llvm-svn: 28918

llvm-svn: 28917

code in sections other than ".text", including weak sections like ctors and
dtors.

llvm-svn: 28909

llvm-svn: 28892

llvm-svn: 28890

llvm-svn: 28889

llvm-svn: 28888

llvm-svn: 28887

llvm-svn: 28886

void test6() {
  Y = 0xABCD0123BCDE4567;
}

into:

_test6:
        lis r2, -21555
        lis r3, ha16(_Y)
        ori r2, r2, 291
        rldicr r2, r2, 32, 31
        oris r2, r2, 48350
        ori r2, r2, 17767
        std r2, lo16(_Y)(r3)
        blr

llvm-svn: 28885

set, so disable the pattern in that case.

llvm-svn: 28884

Split imm16Shifted into a sext/zext form for 64-bit support.
Add some patterns for immediate formation.  For example, we now compile this:

static unsigned long long Y;
void test3() {
  Y = 0xF0F00F00;
}

into:

_test3:
        li r2, 3840
        lis r3, ha16(_Y)
        xoris r2, r2, 61680
        std r2, lo16(_Y)(r3)
        blr

GCC produces:

_test3:
        li r0,0
        lis r2,ha16(_Y)
        ori r0,r0,61680
        sldi r0,r0,16
        ori r0,r0,3840
        std r0,lo16(_Y)(r2)
        blr

llvm-svn: 28883

llvm-svn: 28880

static unsigned long long X, Y;
void test1() {
  X = Y;
}

into:

_test1:
        lis r2, ha16(_Y)
        lis r3, ha16(_X)
        ld r2, lo16(_Y)(r2)
        std r2, lo16(_X)(r3)
        blr

llvm-svn: 28879

removed, tblgen produces identical output to with them in.

llvm-svn: 28867

llvm-svn: 28866

magic to work.

llvm-svn: 28847

llvm-svn: 28841

llvm-svn: 28840